Cambridge IGCSE · Topic 3.1
IGCSE Computer Science 0478 / Topic 3 / IGCSE

Fetch, decode, repeat.

A CPU does one simple thing billions of times a second: it fetches an instruction from memory, works out what it means and carries it out. Follow one instruction through every register and bus on its way.

The key idea

The CPU runs a program by repeating the fetch-decode-execute (FDE) cycle. Fetch: the address in the PC is copied to the MAR and sent along the address bus; the instruction at that address in RAM comes back along the data bus to the MDR and is copied to the CIR; the PC is incremented. Decode: the CU decodes the instruction in the CIR. Execute: the CU sends signals to carry it out, and the ALU does any calculation, with the result stored in the ACC.

FETCHDECODEEXECUTE PC → MAR, read RAMMDR → CIR, PC + 1 CU works out whatthe instruction means CU sends signals;ALU calculates, ACC repeat for the next instruction, once per clock tick (or more) the fetch-decode-execute cycle
Fig. 1: the three stages of the cycle, repeated for every instruction
Section 01

The fetch stage.

Step through the cycle in the lab and watch the values move between registers. Fetching gets the next instruction out of RAM and into the CPU.

  1. The PC holds the address of the next instruction. This address is copied into the MAR.
  2. The address is sent from the MAR to RAM along the address bus; the CU sends a read signal along the control bus.
  3. The instruction stored at that address is sent along the data bus to the MDR.
  4. The instruction is copied from the MDR into the CIR.
  5. The PC is incremented (increased by 1) so it points to the next instruction.
Examiner trap

The PC is incremented during the fetch stage, ready for the next cycle. It is not incremented after the instruction is executed.

Section 02

Decode and execute.

Now the CPU knows what the instruction is, but not yet what it means. The control unit works that out, then makes it happen.

Worked example Trace one instruction
The PC holds 20. Address 20 holds the instruction ADD 26, and address 26 holds the value 5. The ACC holds 7. Describe what happens.
  1. Fetch: 20 is copied from the PC to the MAR and sent along the address bus.
  2. ADD 26 comes back along the data bus to the MDR, then is copied to the CIR. The PC becomes 21.
  3. Decode: the CU decodes ADD 26: add the value at address 26 to the ACC.
  4. Execute: 26 goes to the MAR; the value 5 comes back into the MDR; the ALU adds 7 + 5.
Answer: The ACC holds 12 and the PC holds 21
Your turn
After the fetch stage above, which register holds the instruction ADD 26, and what value is in the PC?
Stage 1 · Learn

Check what the sim just showed you

Four quick checks. Each correct answer earns XP and records this skill on your profile.

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In the lab, where is the address in the PC copied to first?

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Which bus carries the instruction from RAM to the CPU?

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Which component decodes the instruction?

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When is the program counter incremented?

Section 03

Order matters.

Exam questions often ask you to describe the cycle, or to put the steps in order. Each correct step, in the correct order and naming the correct register or bus, earns a mark.

StageRegister or componentWhat happens
FetchPC → MARAddress of the next instruction copied
FetchAddress bus, control busAddress sent to RAM with a read signal
FetchData bus → MDR → CIRInstruction brought into the CPU
FetchPCIncremented
DecodeCUInstruction in the CIR decoded
ExecuteCU, ALU, ACCSignals sent; calculation done; result in ACC
Examiner trap

Name the registers in full or by their correct initials. "It goes to the register" does not earn the mark: say "copied from the MDR to the CIR".

Stage 2 · Exam

Exam-style questions

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Which sequence is correct for the fetch stage?

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An instruction adds two numbers. Where is the result stored?

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Which register holds the instruction while the control unit decodes it?

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The PC holds 45 before an instruction is fetched. What does it hold just after the fetch stage, for a normal instruction?

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Six original Cambridge-style questions
Each stage of the fetch-decode-execute cycle and the registers, buses and units used in it.