IGCSE · Practice questions · The fetch-decode-execute cycle

One instruction at a time.

Six original Cambridge-style questions on the fetch-decode-execute cycle, with mark-scheme style solutions.

Original questions All questions on this page are original work, written in the Cambridge IGCSE style. They are not from past papers. They test the same concepts and skills the syllabus rewards.

Keep these straight

Follow the address.

Fetch: PC → MAR → address bus; data bus → MDR → CIR; PC incremented.
Decode: the CU decodes the instruction in the CIR.
Execute: the CU sends signals; the ALU calculates; the result goes in the ACC.
Marks: one per correct step, in order, naming the register or bus.

Explain

[4 marks]

Describe the stages of the fetch part of the fetch-decode-execute cycle.

The address in the PC is copied to the MAR. ✓
The address is sent to RAM along the address bus (with a read signal on the control bus). ✓
The instruction at that address is sent along the data bus to the MDR. ✓
The instruction is copied from the MDR to the CIR, and the PC is incremented. ✓

Recall

[2 marks]

State what happens during the decode and execute stages.

Decode: the control unit decodes the instruction in the CIR. ✓
Execute: the CU sends signals to carry out the instruction (the ALU performs any calculation and the result is stored in the ACC). ✓

Trace

[3 marks]

The PC holds 30. Address 30 holds the instruction LDA 34, which loads the value at address 34 into the ACC. Address 34 holds 9. State the contents of the PC, the CIR and the ACC after this instruction has been executed.

PC: 31. ✓
CIR: LDA 34. ✓
ACC: 9. ✓

Explain

[2 marks]

Explain why the program counter is incremented during the fetch stage.

So that it holds the address of the next instruction. ✓
Ready for the next fetch, so instructions are run in sequence. ✓

Apply

[2 marks]

Identify the bus used to send the address from the MAR to memory, and the bus used to return the instruction.

Address bus. ✓
Data bus. ✓

Analysis

[2 marks]

A student writes: "In the fetch stage the instruction goes from RAM straight into the CIR." Explain what is missing.

The instruction first arrives in the MDR (along the data bus). ✓
It is then copied from the MDR to the CIR. ✓

Mark this once you have attempted all six and checked your working. It records a Practiced badge on the topic and adds a one-time bonus. Revealing the solutions alone does not count.