Two families of logic circuit sit inside every processor. Adders do binary arithmetic in the ALU; flip-flops store single bits in registers and static RAM. This lesson builds the half adder and full adder, then the SR and JK flip-flops, with their truth tables.
A half adder adds two bits A and B, giving a sum S = A XOR B and a carry C = A AND B. A full adder also adds a carry in, so it can be chained: S = A XOR B XOR Cin and Cout = A.B + Cin.(A XOR B); it can be built from two half adders and an OR gate. A flip-flop is a circuit whose outputs are fed back into its inputs, so it has two stable states and stores one bit. An SR flip-flop is set by S = 1, reset by R = 1, holds its value when S = R = 0, and must not have S = R = 1. A JK flip-flop changes only on a clock pulse and removes the invalid state: J = K = 1 makes it toggle. Flip-flops are the data storage elements of registers and static RAM.
Fig. 1: a full adder. The first half adder adds A and B; the second adds the carry in to their sum; either half adder can produce the carry out
Section 01
Half adders and full adders.
Adding two single bits gives a two-bit answer: 1 + 1 = 10 in binary, a sum of 0 and a carry of 1. Switch the inputs in the lab to see the half adder, the full adder and a 4-bit adder made of full adders.
Half adder (two inputs):
A
B
S
C
0
0
0
0
0
1
1
0
1
0
1
0
1
1
0
1
Full adder (three inputs, including the carry from the column to the right):
A
B
Cin
S
Cout
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
1
1
1
0
0
1
1
1
1
1
1
Half adder circuit: one XOR gate for S and one AND gate for C, both fed by A and B.
Full adder circuit: two half adders and an OR gate (Fig. 1), or directly S = A XOR B XOR Cin and Cout = A.B + Cin.(A XOR B). Cout is 1 whenever at least two of the three inputs are 1.
Why a half adder is not enough: it has no input for a carry, so it can only add the least significant bits.
Multi-bit addition: n full adders are chained, each Cout feeding the next Cin (a ripple-carry adder). A carry out of the most significant adder means the result does not fit: overflow.
Worked example A chain of four full adders
A 4-bit ripple-carry adder adds 0110 and 0111. Give the sum and carry out of each full adder, starting from the least significant bit.
Bit 0: 0 + 1 + carry in 0 = 1, so S = 1, Cout = 0.
Bit 1: 1 + 1 + 0 = 10, so S = 0, Cout = 1.
Bit 2: 1 + 1 + 1 = 11, so S = 1, Cout = 1.
Bit 3: 0 + 0 + 1 = 1, so S = 1, Cout = 0: no overflow.
Answer: 1101 (6 + 7 = 13)
Examiner trap
Do not write the full adder carry as A.B only: a carry in of 1 plus one other 1 also produces a carry. Cout = 1 for rows 011, 101, 110 and 111.
Section 02
The SR flip-flop.
Feed the output of each NOR gate back into the other and the circuit can remember. Toggle S and R in the lab and notice that when both return to 0, Q stays as it was.
S
R
Q before
Q after
Q after
Effect
0
0
0
0
1
no change (memory)
0
0
1
1
0
no change (memory)
1
0
0
1
0
set
1
0
1
1
0
set
0
1
0
0
1
reset
0
1
1
0
1
reset
1
1
0
0
0
not allowed: Q = Q = 0
1
1
1
0
0
not allowed: Q = Q = 0
Set (S = 1, R = 0): Q becomes 1 and Q becomes 0.
Reset (S = 0, R = 1): Q becomes 0.
Hold (S = R = 0): the feedback keeps Q at its previous value. This is the memory.
S = R = 1 forces both outputs to 0, so Q and Q are no longer opposites, and when both inputs return to 0 the final state cannot be predicted. This input must not be used.
An SR flip-flop can also be built from two NAND gates; then the inputs are active low (S and R): 0 sets or resets, 1 and 1 holds, and 0 and 0 is the invalid state.
Worked example Tracing an SR flip-flop
An SR flip-flop made of NOR gates starts with Q = 0. The inputs (S, R) are changed to (1, 0), (0, 0), (0, 1), (0, 0), (1, 0) in turn. Give Q after each change.
Step
S
R
Q
1
1
0
1
2
0
0
1
3
0
1
0
4
0
0
0
5
1
0
1
Steps 2 and 4 (S = R = 0) keep the value set by the step before: that is the stored bit.
Answer: Q = 1, 1, 0, 0, 1
Examiner trap
Saying S = R = 1 "gives Q = 1" loses the mark. For NOR gates both outputs go to 0, which breaks the rule that Q and Q are opposite, so the state is invalid.
Stage 1 · Learn
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What are the outputs of a half adder when A = 1 and B = 1?
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A full adder has A = 1, B = 0 and carry in = 1. What are its outputs?
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An SR flip-flop made of NOR gates has S = 0 and R = 0. What happens to Q?
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In the lab, what does a JK flip-flop do on a clock pulse when J = 1 and K = 1?
Section 03
JK flip-flops and data storage.
The JK flip-flop fixes the two weaknesses of the SR flip-flop: it has no invalid input combination, and it only changes when a clock pulse arrives, so many flip-flops can change together in step.
J
K
Q before pulse
Q after pulse
Effect
0
0
0
0
no change
0
0
1
1
no change
0
1
0
0
reset
0
1
1
0
reset
1
0
0
1
set
1
0
1
1
set
1
1
0
1
toggle
1
1
1
0
toggle
Circuit: an SR flip-flop made of NAND gates, fed by two three-input NAND gates. One combines J, the clock and Q; the other combines K, the clock and Q. The feedback from the outputs is what stops J = K = 1 from being invalid: it makes the flip-flop change to the opposite state.
Clock: the output can only change when a clock pulse arrives (it is synchronous), so all the flip-flops in a register change at the same moment.
Data storage: each flip-flop stores one bit. A register is a group of flip-flops sharing a clock (8 flip-flops hold a byte); static RAM and cache memory are built from flip-flops, which is why SRAM needs no refreshing. Flip-flops are also used in counters and shift registers.
Worked example Tracing a JK flip-flop
A JK flip-flop starts with Q = 0. Six clock pulses arrive with (J, K) = (1, 0), (0, 0), (1, 1), (1, 1), (0, 1), (0, 0). Give Q after each pulse.
Pulse 1: J = 1, K = 0 sets Q to 1. Pulse 2: no change, Q stays 1.
Pulses 3 and 4: J = K = 1 toggles Q, to 0 and then back to 1.
Pulse 5: K = 1, J = 0 resets Q to 0. Pulse 6: no change.
Pulse
J
K
Q
1
1
0
1
2
0
0
1
3
1
1
0
4
1
1
1
5
0
1
0
6
0
0
0
Answer: Q = 1, 1, 0, 1, 0, 0
Your turn
Give two advantages of a JK flip-flop over an SR flip-flop.
It has no invalid state: J = K = 1 toggles the output instead. It is clocked, so its output changes only on a clock pulse and many flip-flops (for example in a register) change in step.
Examiner trap
"A flip-flop stores data" is too vague. Say it stores one bit, and name a use: registers, static RAM or cache.
Stage 2 · Exam
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Which pair of expressions describes a full adder?
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Why are flip-flops used in registers?
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Which input combination must NOT be used on an SR flip-flop made of NOR gates?
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Why can a half adder not be used for every column of a multi-bit addition?
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