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A2 · Practice questions · Half adders, full adders and flip-flops

Add, carry, store.

Six original Cambridge-style questions on half and full adder truth tables and circuits, SR and JK flip-flops and their role in data storage, with mark-scheme style solutions.

Original questions All questions on this page are original work, written in the Cambridge AS & A Level style. They are not from past papers. They test the same concepts and skills the syllabus rewards.
How to earn the marks

Table first, then explain.

01
Recall
[4 marks]

Complete the truth table for a half adder, and state the logic gate that produces each output.

  • The S column for inputs 00, 01, 10, 11 is 0, 1, 1, 0. ✓
  • The C column for inputs 00, 01, 10, 11 is 0, 0, 0, 1. ✓
  • S is produced by an XOR gate. ✓
  • C is produced by an AND gate. ✓
02
Write
[4 marks]

Complete the truth table for a full adder with inputs A, B and Cin, and outputs S and Cout.

  • Inputs listed 000 to 111. ✓
  • S column: 0, 1, 1, 0, 1, 0, 0, 1 (1 when an odd number of inputs are 1). ✓
  • Cout column: 0, 0, 0, 1, 0, 1, 1, 1 (1 when at least two inputs are 1). ✓
  • One mark for each correct pair of rows, as in the table:
    ABCinSCout
    00000
    00110
    01010
    01101
    10010
    10101
    11001
    11111
    ✓
03
Explain
[3 marks]

Describe how a full adder can be built from two half adders.

  • The first half adder adds A and B, giving a partial sum and a carry. ✓
  • The second half adder adds the partial sum and Cin; its sum output is S. ✓
  • The two carry outputs are combined with an OR gate to give Cout. ✓
04
Trace
[3 marks]

A 4-bit ripple-carry adder adds 1011 and 0110. Give the result, the final carry out, and state what the final carry shows.

  • Sum bits from the left: 0001. ✓
  • Carries out of bits 0 to 3: 0, 1, 1, 1, so the final carry out is 1. ✓
  • The true result (11 + 6 = 17 = 10001) needs five bits: the final carry shows an overflow. ✓
05
Explain
[4 marks]

An SR flip-flop is built from two NOR gates. Explain how it stores one bit of data, and why the input S = 1, R = 1 is not used.

  • The output of each NOR gate is fed back as an input to the other gate. ✓
  • S = 1 sets Q to 1 and R = 1 resets Q to 0. ✓
  • When S = R = 0 the feedback keeps Q at its last value, so the bit is stored. ✓
  • S = R = 1 makes both Q and Q equal 0, so they are not complements and the next state is unpredictable (invalid). ✓
06
Trace
[3 marks]

A JK flip-flop starts with Q = 1. Clock pulses arrive with (J, K) = (0, 0), (1, 1), (0, 1), (1, 1). Give Q after each pulse and explain the role of the clock.

  • Q after the pulses: 1, 0, 0, 1. ✓
  • J = K = 1 toggles Q; J = 0, K = 1 resets it; J = K = 0 leaves it unchanged. ✓
  • The output only changes when a clock pulse arrives, so all flip-flops in a register change together (synchronously). ✓

Mark this once you have attempted all six and checked your working. It records a Practiced badge on the topic and adds a one-time bonus. Revealing the solutions alone does not count.