Processor designers face a choice: give the CPU a few simple instructions that each finish in one clock cycle, or many powerful instructions that take several. This lesson compares RISC and CISC, shows how pipelining and a large set of registers make RISC fast, and explains what happens to a pipeline when an interrupt arrives.
A RISC (Reduced Instruction Set Computer) processor has a small set of simple, fixed-length instructions, most of which execute in one clock cycle; only LOAD and STORE instructions access memory, and all other operations work on registers, so a RISC processor has many general-purpose registers. A CISC (Complex Instruction Set Computer) processor has a large set of complex, variable-length instructions, many of which take several clock cycles and can work directly on memory. Because RISC instructions are uniform, they suit pipelining: the fetch-execute cycle is split into stages, and while one instruction is being executed the next ones are already being decoded and fetched, so once the pipeline is full one instruction completes every clock cycle. An interrupt in a pipelined processor means the partly processed instructions must either be allowed to finish or be flushed before the interrupt service routine runs.
Fig. 1: a five-stage pipeline (instruction fetch, instruction decode, operand fetch, instruction execute, write back). Each instruction still takes five cycles, but a new one starts every cycle.
Section 01
RISC against CISC.
The two designs make opposite trade-offs. CISC puts the complexity in the hardware so that one instruction does a lot of work; RISC keeps the hardware simple and fast and lets the compiler build complex operations from many simple instructions.
Feature
RISC
CISC
Instruction set
Fewer, simpler instructions
Many instructions, some very complex
Instruction format
Fixed length, few formats
Variable length, many formats
Clock cycles per instruction
Most take one cycle
Many take several cycles
Addressing modes
Few
Many
Memory access
Only LOAD and STORE use memory (load/store design); other instructions work on registers
Many instructions can use operands held in memory directly
Registers
Many general-purpose registers
Fewer general-purpose registers
Control unit
Usually hardwired
Usually microprogrammed
Pipelining
Easy: every instruction has the same length and timing
Harder: instructions vary in length and time
Programs
More instructions per program, more work for the compiler, more RAM for the code
Fewer instructions per program, closer to high-level statements
Typical use
ARM processors in phones, tablets and embedded devices (low power)
x86 processors in most desktop and laptop PCs
Worked example One task, two designs
Two values held in memory must be multiplied and the result stored back in memory. Compare how a CISC and a RISC processor do this.
CISC: a single complex instruction fetches both operands from memory, multiplies them and stores the result. It is one instruction, but it takes several clock cycles.
RISC: LOAD the first value into a register, LOAD the second value into another register, MULTIPLY the two registers, STORE the result. Four simple instructions.
Each RISC instruction takes about one clock cycle and has the same format, so the four can be pipelined and overlap.
The RISC program is longer (more memory for the code) and the compiler does more work; the CISC hardware is more complex.
Answer: CISC: fewer instructions, each taking several cycles. RISC: more instructions, each taking one cycle and suited to pipelining
Examiner trap
Do not say RISC processors "cannot do" complex operations. They do them with a sequence of simple instructions. The difference is where the complexity lives: in the hardware (CISC) or in the compiler and program (RISC).
Section 02
Pipelining and registers.
Without pipelining, the processor finishes every stage of one instruction before it starts the next, so most of its hardware is idle most of the time. Pipelining keeps every stage busy, like an assembly line.
Pipelining: instruction-level parallelism. The fetch-execute cycle is split into stages, and different instructions are at different stages at the same time. A typical five-stage pipeline is IF (instruction fetch), ID (instruction decode), OF (operand fetch), IE (instruction execute) and WB (write back the result).
The timing: with k stages of one clock cycle each, n instructions take k × n cycles without pipelining but only k + n − 1 cycles with it. Once the pipeline is full, one instruction finishes every cycle.
Why RISC suits it: fixed-length instructions that each take one cycle per stage keep the stages in step. A CISC instruction that needs ten cycles to execute would hold up every instruction behind it.
Why registers matter: RISC processors have many general-purpose registers, so operands are kept in registers rather than fetched from slower memory; register-to-register operations take the same short time, which keeps the pipeline flowing. Each stage also needs its own registers (buffers) to pass the partly processed instruction on to the next stage.
Worked example Counting clock cycles
A processor has a five-stage pipeline and each stage takes one clock cycle. How many cycles are needed to execute 6 instructions with and without pipelining?
Without pipelining each instruction uses all 5 stages before the next starts: 6 × 5 = 30 cycles.
With pipelining the first instruction finishes after 5 cycles.
After that, one more instruction finishes every cycle, so the other 5 instructions need 5 more cycles.
Total with pipelining: 5 + 6 − 1 = 10 cycles.
Answer: 30 cycles without pipelining, 10 cycles with pipelining (three times faster here)
Your turn
The same processor executes 100 instructions. How many clock cycles does it need with and without pipelining?
Without: 100 × 5 = 500 cycles. With: 5 + 100 − 1 = 104 cycles, so for a long run the speed-up approaches the number of stages (5).
Examiner trap
Pipelining does not make a single instruction faster: each one still passes through all five stages. It increases throughput, the number of instructions completed per second. A jump or a branch can also force the instructions already fetched behind it to be flushed, wasting cycles.
Stage 1 · Learn
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Which feature is typical of a RISC processor?
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Why does a RISC processor have a large number of general-purpose registers?
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A five-stage pipeline executes 6 instructions, one stage per clock cycle. How many cycles does it take?
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An interrupt arrives while a pipelined RISC processor has several instructions in progress. Which is one correct way to handle it?
Section 03
Interrupts in a pipeline.
On any processor, an interrupt makes the CPU save its current state, run an interrupt service routine (ISR) and then carry on where it left off. Pipelining complicates the "where it left off" part, because several instructions are half finished. Revisit the basic sequence in the lab.
CISC processor
RISC processor with a pipeline
When is the interrupt checked?
At the end of each fetch-execute cycle, so a long multi-cycle instruction can delay the response.
Every cycle an instruction completes, but up to five instructions are in the pipeline at once.
What happens to the instructions in progress?
Only one instruction is in progress; it is finished first.
Either the instructions in the pipeline are flushed (discarded and fetched again later), or those already started are allowed to complete before the ISR is loaded.
What must be saved?
The program counter and the other registers, on the stack.
The program counter (the address of the first instruction that did not complete) and the registers, and, if instructions are kept, the pipeline state.
After the ISR
Registers are restored and the next instruction is fetched.
Registers are restored and the pipeline refills from the saved address.
Your turn
Explain why handling an interrupt is more complicated on a pipelined RISC processor than on a non-pipelined CISC processor.
In a pipeline several instructions are partly processed at the moment of the interrupt, so the processor must either flush them (and refetch them later from a saved program counter value) or let them finish first; it must save enough state to restart in exactly the right place. A non-pipelined CISC processor only has one instruction in progress.
Examiner trap
When a pipeline is flushed, the discarded instructions are not lost: the saved program counter points to the first one that did not complete, so they are fetched again after the ISR.
Stage 2 · Exam
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Which statement correctly compares RISC and CISC?
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What is the main benefit of pipelining?
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A four-stage pipeline executes 10 instructions, one stage per clock cycle. How many clock cycles are saved compared with no pipelining?
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Why can a long CISC instruction delay the response to an interrupt?
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