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A2 · Practice questions · RISC and CISC processors and pipelining

Keep the pipeline full.

Six original Cambridge-style questions on RISC and CISC processors, pipeline cycle counts, the role of registers and interrupts in a pipelined processor, with mark-scheme style solutions.

Original questions All questions on this page are original work, written in the Cambridge AS & A Level style. They are not from past papers. They test the same concepts and skills the syllabus rewards.
How to earn the marks

Compare, then explain why.

01
Recall
[4 marks]

State four differences between RISC and CISC processors.

  • RISC has fewer, simpler instructions; CISC has many, more complex instructions. ✓
  • RISC instructions are fixed length; CISC instructions are variable length. ✓
  • Most RISC instructions take one clock cycle; many CISC instructions take several. ✓
  • Any one of: RISC uses only LOAD and STORE to access memory, CISC instructions can use memory operands; RISC has more general-purpose registers; RISC has fewer addressing modes; RISC is easier to pipeline; RISC control units are hardwired, CISC microprogrammed. ✓
02
Calculate
[3 marks]

A RISC processor has a five-stage pipeline: IF, ID, OF, IE, WB. Each stage takes one clock cycle. Calculate how many clock cycles it takes to execute 12 instructions, with and without pipelining, and state how many cycles are saved.

  • Without pipelining: 12 × 5 = 60 cycles. ✓
  • With pipelining: 5 + 12 − 1 = 16 cycles. ✓
  • Saving: 60 − 16 = 44 cycles. ✓
03
Explain
[3 marks]

Explain how pipelining improves the performance of a processor.

  • The execution of an instruction is split into stages (such as fetch, decode, operand fetch, execute, write back). ✓
  • While one instruction is at one stage, other instructions are at the other stages at the same time. ✓
  • Once the pipeline is full, one instruction completes every clock cycle, so more instructions are completed per second (higher throughput). ✓
04
Explain
[3 marks]

Explain why registers are important in a RISC processor.

  • RISC uses a load/store design: only LOAD and STORE access memory, other instructions operate on registers. ✓
  • Having many general-purpose registers means operands are held in registers, reducing the number of slow memory accesses. ✓
  • Register-to-register instructions all take the same short time, which keeps a pipeline flowing; registers between stages pass each partly processed instruction on. ✓
05
Explain
[4 marks]

Describe how an interrupt is handled by a RISC processor that uses pipelining.

  • Several instructions are partly processed in the pipeline when the interrupt is received. ✓
  • The instructions in the pipeline are flushed, or those already started are allowed to complete. ✓
  • The program counter (address of the next instruction not completed) and the contents of the registers are saved on the stack. ✓
  • The ISR is loaded and executed; afterwards the registers are restored and the pipeline is refilled from the saved address. ✓
06
Analysis
[3 marks]

A program contains a conditional jump. When the jump is taken, the processor's performance drops. Explain why, with reference to the pipeline.

  • Instructions following the jump in memory have already been fetched (and partly decoded) into the pipeline. ✓
  • If the jump is taken, those instructions are the wrong ones and must be flushed. ✓
  • The pipeline has to refill from the jump target, so several clock cycles pass without an instruction completing. ✓

Mark this once you have attempted all six and checked your working. It records a Practiced badge on the topic and adds a one-time bonus. Revealing the solutions alone does not count.