Every instruction a processor runs starts with the same four register transfers. At AS Level you describe them in register transfer notation, a short and exact way of saying which value moves into which register. Learn to read it, write it and use it to trace an instruction.
The fetch-execute (F-E) cycle is repeated for every instruction. In register transfer notation, [X] means the contents of X and ← means is copied into. The fetch stage is: MAR ← [PC]; PC ← [PC] + 1; MDR ← [[MAR]]; CIR ← [MDR]. The control unit then decodes the instruction in the CIR and it is executed, which may use memory again through the MAR and MDR and the ALU.
Fig. 1: the four register transfers of the fetch stage
Section 01
Reading the notation.
Step through the cycle in the lab: each step shows its register transfer. The notation is compact, so read every bracket carefully.
Notation
Meaning
MAR ← [PC]
The contents of the PC (an address) are copied into the MAR.
PC ← [PC] + 1
The PC is incremented, so it holds the address of the following instruction.
MDR ← [[MAR]]
The contents of the memory location whose address is in the MAR are copied into the MDR. The double brackets mean "the contents of the address held in the MAR".
CIR ← [MDR]
The instruction in the MDR is copied into the CIR, ready to be decoded.
Examiner trap
MDR ← [MAR] is wrong: it would copy the address itself. The instruction comes from the memory location the MAR points to, so it is MDR ← [[MAR]].
Section 02
Fetch, decode, execute.
Describe the cycle in full sentences when asked to "describe", and in notation when the question asks for register transfer notation. Both earn the same marks for the same steps.
Fetch: the address in the PC is copied to the MAR. The address is sent along the address bus and a read signal along the control bus.
The PC is incremented. (This can happen while the memory is being read.)
The instruction at that address is sent along the data bus into the MDR, then copied to the CIR.
Decode: the control unit decodes the instruction in the CIR into its opcode and operand.
Execute: the CU sends control signals. If data is needed from memory, the operand address goes to the MAR and the data comes back into the MDR; the ALU does any arithmetic or logic and the result goes into the ACC. A jump instruction copies its address into the PC.
The processor checks for interrupts, then the cycle repeats.
Instruction
Execute stage in register transfer notation
LDD 150
MAR ← 150; MDR ← [[MAR]]; ACC ← [MDR]
ADD 151
MAR ← 151; MDR ← [[MAR]]; ACC ← [ACC] + [MDR]
JMP 120
PC ← 120
Examiner trap
The PC is incremented in the fetch stage, not after the instruction has been executed. This is why a jump instruction simply overwrites the PC.
Stage 1 · Learn
Check what the sim just showed you
Four quick checks. Each correct answer earns XP and records this skill on your profile.
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What does MDR ← [[MAR]] mean?
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In the lab, which transfer comes first in the fetch stage?
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Which register holds the instruction while it is decoded?
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What does PC ← [PC] + 1 do?
Section 03
Trace one instruction.
A common question gives you the PC and the contents of memory, then asks for the value in each register after a step. Work through the four fetch transfers in order, then the execute stage.
Worked example LDD 150
The PC holds 100. Address 100 holds the instruction LDD 150 and address 150 holds 37. Give the contents of the PC, MAR, MDR, CIR and ACC after the instruction has been executed.
MAR ← [PC]: the MAR holds 100.
PC ← [PC] + 1: the PC holds 101.
MDR ← [[MAR]]: the MDR holds the instruction LDD 150. CIR ← [MDR]: the CIR holds LDD 150.
Execute: the operand 150 is copied to the MAR, so the MAR holds 150. MDR ← [[MAR]]: the MDR holds 37.
ACC ← [MDR]: the ACC holds 37.
Answer: PC 101, MAR 150, MDR 37, CIR LDD 150, ACC 37
Your turn
The next instruction, at address 101, is ADD #5. Give the contents of the PC, CIR and ACC after it has been executed. Is the MAR used in the execute stage?
PC 102, CIR ADD #5, ACC 42 (37 + 5). The MAR is not used in the execute stage, because #5 is immediate: the value is in the instruction itself, so memory is not accessed again. (The MAR still holds 101 from the fetch.)
Stage 2 · Exam
Exam-style questions
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Which is the correct order of the fetch stage?
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The PC holds 230 before an instruction is fetched. The instruction is JMP 300. What does the PC hold after it has been executed?
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During the execute stage of ADD 151, which transfer adds the value from memory?
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When are interrupts checked in the cycle?
Skill unlocked
The fetch-execute cycle in register transfer notation, mastered.
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