Six original Cambridge-style questions on the fetch-execute cycle and register transfer notation, with mark-scheme style solutions.
Complete the fetch stage of the fetch-execute cycle using register transfer notation.
Explain the difference between [MAR] and [[MAR]] in register transfer notation.
The PC holds 40. Address 40 holds LDD 60 and address 60 holds 18. State the contents of the PC, MAR, MDR, CIR and ACC after the instruction has been fetched and executed.
Describe what happens during the decode and execute stages of the cycle for the instruction ADD 75.
Write the execute stage of the instruction JMP 85 in register transfer notation, and explain why the earlier PC ← [PC] + 1 does not cause a problem.
A student writes the fetch stage as: MAR ← [PC]; MDR ← [MAR]; CIR ← [MDR]. Identify the two errors.
Mark this once you have attempted all six and checked your working. It records a Practiced badge on the topic and adds a one-time bonus. Revealing the solutions alone does not count.