The shape of the lesson
By the end of the lesson, learners can
- Half adders and full adders: Adding two single bits gives a two-bit answer: 1 + 1 = 10 in binary, a sum of 0 and a carry of 1.
- The SR flip-flop: Feed the output of each NOR gate back into the other and the circuit can remember.
- JK flip-flops and data storage: The JK flip-flop fixes the two weaknesses of the SR flip-flop: it has no invalid input combination, and it only changes when a clock pulse arrives, so many flip-flops can change together in step.
- Adders: S is XOR of the inputs; the carry is 1 when at least two inputs are 1.
- Circuits: a full adder is two half adders plus an OR gate on the two carries.
- SR: set, reset, hold (no change), and say why S = R = 1 is invalid.
- JK: clocked; J = K = 1 toggles; stores one bit, used in registers and SRAM.
One picture every idea returns to
A half adder adds two bits A and B, giving a sum S = A XOR B and a carry C = A AND B. A full adder also adds a carry in, so it can be chained: S = A XOR B XOR Cin and Cout = A.B + Cin.(A XOR B); it can be built from two half adders and an OR gate. A flip-flop is a circuit whose outputs are fed back into its inputs, so it has two stable states and stores one bit. An SR flip-flop is set by S = 1, reset by R = 1, holds its value when S = R = 0, and must not have S = R = 1. A JK flip-flop changes only on a clock pulse and removes the invalid state: J = K = 1 makes it toggle. Flip-flops are the data storage elements of registers and static RAM.
Forty-five minutes, phase by phase
| Time | Phase | What happens in the room | Grouping |
|---|---|---|---|
| 0 to 5 min | Hook: predict | Open with the question in the title, Circuits that add and remember.. Two families of logic circuit sit inside every processor. Put the figure on the board: it is the one picture every idea in the lesson returns to. | Whole class, then pairs |
| 5 to 13 min | Teach and check: Half adders and full adders | Adding two single bits gives a two-bit answer: 1 + 1 = 10 in binary, a sum of 0 and a carry of 1. Project tab 5 of the lab (Half adder, full adder and 4-bit adder) and let a student drive it while the class predicts. Model the worked example A chain of four full adders on the board, one line at a time. | Whole class, then pairs |
| 13 to 21 min | Teach and check: The SR flip-flop | Feed the output of each NOR gate back into the other and the circuit can remember. Project tab 6 of the lab (SR and JK flip-flops) and let a student drive it while the class predicts. Model the worked example Tracing an SR flip-flop on the board, one line at a time. | Pairs |
| 21 to 30 min | Teach and check: JK flip-flops and data storage | The JK flip-flop fixes the two weaknesses of the SR flip-flop: it has no invalid input combination, and it only changes when a clock pulse arrives, so many flip-flops can change together in step. Model the worked example Tracing a JK flip-flop on the board, one line at a time. Your turn: Give two advantages of a JK flip-flop over an SR flip-flop. | Think-Pair-Share |
| 30 to 36 min | Check | The four Stage 1 questions from the student lesson, answered on mini whiteboards or by show of fingers. Re-teach the one most get wrong. | Individual, then whole class |
| 36 to 43 min | Plenary | The exam-style questions from Stage 2, one at a time: thirty seconds alone, then a random call. The feedback lines in the key give the examiner's wording. | Individual, random call |
| 43 to 45 min | Exit and homework | Set the worksheet below (6 questions, 21 marks). Learners self-assess against the objectives before they leave. | Individual |
Protect the parts that carry the learning
The sequence carries about fifty minutes of material, so the lab is driven by one student while the class predicts rather than explored freely. Times are a guide.
Protected: the check at 30 minutes. It is the only individual read on whether the key idea landed, and it is not cut.
Cut first if the build overruns: the last check in JK flip-flops and data storage, never the check or the plenary.
In a 60 minute block: run worksheet questions 1 to 3 in class as a Rally Coach set and model both the hardest worked example and its check live.
Think-Pair-Share
Pose the question, give thirty seconds of silent thinking, then a minute to compare with a partner before a few pairs share with the class. The silent minute is the part that cannot be cut.
The full structure, with its variations and the other twelve, is on the cooperative-learning page.
What to head off, and how
| Trap learners fall into | Teaching move that pre-empts it |
|---|---|
| Do not write the full adder carry as A.B only: a carry in of 1 plus one other 1 also produces a carry. | C out = 1 for rows 011, 101, 110 and 111. |
| Saying S = R = 1 "gives Q = 1" loses the mark. | For NOR gates both outputs go to 0, which breaks the rule that Q and Q are opposite, so the state is invalid. |
| "A flip-flop stores data" is too vague. | Say it stores one bit, and name a use: registers, static RAM or cache. |
Half adders, full adders and flip-flops: worksheet
6 questions, 21 marks. Written in the style of the papers; no past paper question is reproduced.
Complete the truth table for a half adder, and state the logic gate that produces each output.
Complete the truth table for a full adder with inputs A, B and Cin, and outputs S and Cout.
Describe how a full adder can be built from two half adders.
A 4-bit ripple-carry adder adds 1011 and 0110. Give the result, the final carry out, and state what the final carry shows.
An SR flip-flop is built from two NOR gates. Explain how it stores one bit of data, and why the input S = 1, R = 1 is not used.
A JK flip-flop starts with Q = 1. Clock pulses arrive with (J, K) = (0, 0), (1, 1), (0, 1), (1, 1). Give Q after each pulse and explain the role of the clock.
Answer key and marking notes
- The S column for inputs 00, 01, 10, 11 is 0, 1, 1, 0.
- The C column for inputs 00, 01, 10, 11 is 0, 0, 0, 1.
- S is produced by an XOR gate.
- C is produced by an AND gate.
- Inputs listed 000 to 111.
- S column: 0, 1, 1, 0, 1, 0, 0, 1 (1 when an odd number of inputs are 1).
- Cout column: 0, 0, 0, 1, 0, 1, 1, 1 (1 when at least two inputs are 1).
- One mark for each correct pair of rows, as in the table:
A B Cin S Cout 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1
- The first half adder adds A and B, giving a partial sum and a carry.
- The second half adder adds the partial sum and Cin; its sum output is S.
- The two carry outputs are combined with an OR gate to give Cout.
- Sum bits from the left: 0001.
- Carries out of bits 0 to 3: 0, 1, 1, 1, so the final carry out is 1.
- The true result (11 + 6 = 17 = 10001) needs five bits: the final carry shows an overflow.
- The output of each NOR gate is fed back as an input to the other gate.
- S = 1 sets Q to 1 and R = 1 resets Q to 0.
- When S = R = 0 the feedback keeps Q at its last value, so the bit is stored.
- S = R = 1 makes both Q and Q equal 0, so they are not complements and the next state is unpredictable (invalid).
- Q after the pulses: 1, 0, 0, 1.
- J = K = 1 toggles Q; J = 0, K = 1 resets it; J = K = 0 leaves it unchanged.
- The output only changes when a clock pulse arrives, so all flip-flops in a register change together (synchronously).
6 multiple-choice questions on this lesson
From the topic question bank. Assign them in the app for a marked score in your gradebook, or run the topic as a class game.
A half adder has inputs A and B, a sum output S and a carry output C. Which gates produce S and C?
- AS from an XOR gate, C from an AND gate
- BS from an OR gate, C from an AND gate
- CS from an AND gate, C from an XOR gate
- DS from an XOR gate, C from an OR gate
A full adder has inputs A = 1, B = 1 and Cin = 1. What are its outputs?
- AS = 1, Cout = 1
- BS = 0, Cout = 1
- CS = 1, Cout = 0
- DS = 0, Cout = 0
An SR flip-flop built from two NOR gates starts with Q = 1. The inputs (S, R) are changed to (0, 1), (0, 0), (1, 0), (0, 0), (0, 1) in turn. What is Q after each change?
- A0, 0, 1, 1, 0
- B0, 1, 1, 0, 0
- C0, 0, 1, 0, 0
- D1, 1, 0, 0, 1
Which statement describes the role of flip-flops in data storage?
- AEach flip-flop stores one bit, and registers and static RAM are built from them
- BEach flip-flop stores one byte, and the computer's secondary storage is built from them
- CEach flip-flop stores one bit only while it is refreshed, as in dynamic RAM
- DEach flip-flop stores one bit permanently, even with the power off, as in flash memory
A 4-bit ripple-carry adder, made of four full adders, adds 1001 and 0111. What are the four sum bits and the carry out of the most significant full adder?
- ASum 0000, final carry out 1
- BSum 1110, final carry out 0
- CSum 0000, final carry out 0
- DSum 1111, final carry out 0
A JK flip-flop starts with Q = 0. Six clock pulses arrive with (J, K) = (1, 1), (1, 1), (0, 0), (1, 0), (1, 1), (0, 1). What is Q after each pulse?
- A1, 0, 0, 1, 0, 0
- B1, 1, 1, 1, 1, 0
- C1, 0, 1, 1, 0, 0
- D0, 0, 0, 1, 0, 0
Quiz key
The sum column is 0, 1, 1, 0, which is XOR, and the carry column is 0, 0, 0, 1, which is AND (1 + 1 = 10). OR would give a sum of 1 for 1 + 1, which is wrong; swapping the gates puts the carry in the sum column; and an OR carry would give a carry for 0 + 1.
1 + 1 + 1 = 3 = 11 in binary, so the sum bit is 1 and the carry out is 1. S = 0, Cout = 1 is the answer for only two 1s (1 + 1 = 10). S = 1 with no carry would mean the total was 1, and 0 with no carry ignores the inputs altogether.
(0, 1) resets Q to 0; (0, 0) holds 0; (1, 0) sets Q to 1; (0, 0) holds 1; (0, 1) resets to 0, giving 0, 0, 1, 1, 0. 0, 1, 1, 0, 0 treats S = R = 0 as a toggle, 0, 0, 1, 0, 0 treats it as a reset, and 1, 1, 0, 0, 1 swaps the roles of S and R. Holding the previous value when S = R = 0 is what lets the flip-flop store a bit.
A flip-flop has two stable states, so it holds one bit for as long as it has power; registers (for example 8 flip-flops for a byte), cache and static RAM are made of them. One flip-flop holds a bit, not a byte, and is far too expensive for secondary storage. Dynamic RAM uses capacitors that need refreshing, and flip-flops lose their data when the power is off, unlike flash memory.
Bit 0: 1 + 1 = 10 (sum 0, carry 1). Bit 1: 0 + 1 + 1 = 10 (sum 0, carry 1). Bit 2: 0 + 1 + 1 = 10 (sum 0, carry 1). Bit 3: 1 + 0 + 1 = 10 (sum 0, carry 1). So the sum bits are 0000 with a final carry of 1: 9 + 7 = 16 needs five bits, an overflow. 1110 is the XOR of the inputs with every carry ignored, 1111 is their OR, and 0000 with no carry loses the final carry that shows the overflow.
(1, 1) toggles 0 to 1, (1, 1) toggles back to 0, (0, 0) holds 0, (1, 0) sets 1, (1, 1) toggles to 0 and (0, 1) resets to 0, giving 1, 0, 0, 1, 0, 0. 1, 1, 1, 1, 1, 0 treats J = K = 1 as a set, 1, 0, 1, 1, 0, 0 treats J = K = 0 as a toggle, and 0, 0, 0, 1, 0, 0 treats J = K = 1 as a reset. Toggling is how the JK flip-flop removes the invalid state of the SR flip-flop.
What to project
The student lesson embeds these tabs. Open them full screen on the projector; every slider has a drag handle on the stage.
Slides for this lesson
A projectable deck for every pack is on the way. Until then, present the student lesson full screen: its sections, figure and lab tabs follow the same order as the plan above.