Unit at a glance
6 lessons, 270 minutes of teaching
Scheme of work
The lessons in order
| Ref | Lesson pack | Structure | Worksheet | Quiz | Lab tab |
|---|---|---|---|---|---|
| 15.1 | RISC and CISC processors and pipelining Processor designers face a choice: give the CPU a few simple instructions that each finish in one clock cycle, or many powerful instructions that take several. | Corners | 6 Q, 20 marks | 6 MCQ | tab 7 |
| 15.1 | Parallel processing architectures Computers are classified by how many instruction streams and data streams they handle at once. | Frayer Model | 6 Q, 19 marks | 6 MCQ | tab 3 |
| 15.1 | Virtual machines A virtual machine is software that behaves like a complete computer, so one physical machine can run several operating systems at once. | Connect-Extend-Challenge | 6 Q, 17 marks | 6 MCQ | none |
| 15.2 | Boolean algebra Boolean algebra lets you rewrite a logic expression into a simpler one that gives exactly the same truth table, so the circuit needs fewer gates. | Anticipation / Reaction Guide | 6 Q, 17 marks | 6 MCQ | tab 2 |
| 15.2 | Karnaugh maps A Karnaugh map lays out a truth table as a grid in which neighbouring cells differ by just one input. | Cooperative Concept Mapping | 6 Q, 18 marks | 6 MCQ | tab 7 |
| 15.2 | Half adders, full adders and flip-flops Two families of logic circuit sit inside every processor. | Think-Pair-Share | 6 Q, 21 marks | 6 MCQ | tab 5, tab 6 |
Each pack holds the plan, worksheet and quiz for its lesson. Teach the rows in order; the lab tabs match the student lessons.
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