The shape of the lesson
By the end of the lesson, learners can
- RISC against CISC: The two designs make opposite trade-offs.
- Pipelining and registers: Without pipelining, the processor finishes every stage of one instruction before it starts the next, so most of its hardware is idle most of the time.
- Interrupts in a pipeline: On any processor, an interrupt makes the CPU save its current state, run an interrupt service routine (ISR) and then carry on where it left off.
- Differences: give each one as a matched pair, saying what RISC does and what CISC does.
- Pipelining: name the stages and say that different instructions are at different stages at the same time.
- Cycle counts: k × n without a pipeline, k + n − 1 with one; show both before subtracting.
- Interrupts: flush or complete the pipeline, save the PC and registers, run the ISR, restore and refill.
One picture every idea returns to
A RISC (Reduced Instruction Set Computer) processor has a small set of simple, fixed-length instructions, most of which execute in one clock cycle; only LOAD and STORE instructions access memory, and all other operations work on registers, so a RISC processor has many general-purpose registers. A CISC (Complex Instruction Set Computer) processor has a large set of complex, variable-length instructions, many of which take several clock cycles and can work directly on memory. Because RISC instructions are uniform, they suit pipelining: the fetch-execute cycle is split into stages, and while one instruction is being executed the next ones are already being decoded and fetched, so once the pipeline is full one instruction completes every clock cycle. An interrupt in a pipelined processor means the partly processed instructions must either be allowed to finish or be flushed before the interrupt service routine runs.
Forty-five minutes, phase by phase
| Time | Phase | What happens in the room | Grouping |
|---|---|---|---|
| 0 to 5 min | Hook: predict | Open with the question in the title, Simple instructions, faster processors.. Processor designers face a choice: give the CPU a few simple instructions that each finish in one clock cycle, or many powerful instructions that take several. Put the figure on the board: it is the one picture every idea in the lesson returns to. | Whole class, then pairs |
| 5 to 13 min | Teach and check: RISC against CISC | The two designs make opposite trade-offs. Model the worked example One task, two designs on the board, one line at a time. | Whole class, then pairs |
| 13 to 21 min | Teach and check: Pipelining and registers | Without pipelining, the processor finishes every stage of one instruction before it starts the next, so most of its hardware is idle most of the time. Model the worked example Counting clock cycles on the board, one line at a time. Your turn: The same processor executes 100 instructions. How many clock cycles does it need with and without pipelining? | Pairs |
| 21 to 30 min | Teach and check: Interrupts in a pipeline | On any processor, an interrupt makes the CPU save its current state, run an interrupt service routine (ISR) and then carry on where it left off. Project tab 7 of the lab (Interrupts and the interrupt service routine) and let a student drive it while the class predicts. Your turn: Explain why handling an interrupt is more complicated on a pipelined RISC processor than on a non-pipelined CISC processor. | Corners |
| 30 to 36 min | Check | The four Stage 1 questions from the student lesson, answered on mini whiteboards or by show of fingers. Re-teach the one most get wrong. | Individual, then whole class |
| 36 to 43 min | Plenary | The exam-style questions from Stage 2, one at a time: thirty seconds alone, then a random call. The feedback lines in the key give the examiner's wording. | Individual, random call |
| 43 to 45 min | Exit and homework | Set the worksheet below (6 questions, 20 marks). Learners self-assess against the objectives before they leave. | Individual |
Protect the parts that carry the learning
The sequence carries about fifty minutes of material, so the lab is driven by one student while the class predicts rather than explored freely. Times are a guide.
Protected: the check at 30 minutes. It is the only individual read on whether the key idea landed, and it is not cut.
Cut first if the build overruns: the last check in Interrupts in a pipeline, never the check or the plenary.
In a 60 minute block: run worksheet questions 1 to 3 in class as a Rally Coach set and model both the hardest worked example and its check live.
Corners
Put one answer or viewpoint in each corner of the room. Students move to the corner they agree with, justify the choice to a partner there, then hear one voice from each corner before the reveal.
The full structure, with its variations and the other twelve, is on the cooperative-learning page.
What to head off, and how
| Trap learners fall into | Teaching move that pre-empts it |
|---|---|
| Do not say RISC processors "cannot do" complex operations. | They do them with a sequence of simple instructions. The difference is where the complexity lives: in the hardware (CISC) or in the compiler and program (RISC). |
| Pipelining does not make a single instruction faster: each one still passes through all five stages. | It increases throughput, the number of instructions completed per second. A jump or a branch can also force the instructions already fetched behind it to be flushed, wasting cycles. |
| When a pipeline is flushed, the discarded instructions are not lost: the saved program counter points to the first one that did not complete, so they are fetched again after the ISR. | Return to Interrupts in a pipeline: ask a pair to state the correct version and show it on the lab before moving on. |
RISC and CISC processors and pipelining: worksheet
6 questions, 20 marks. Written in the style of the papers; no past paper question is reproduced.
State four differences between RISC and CISC processors.
A RISC processor has a five-stage pipeline: IF, ID, OF, IE, WB. Each stage takes one clock cycle. Calculate how many clock cycles it takes to execute 12 instructions, with and without pipelining, and state how many cycles are saved.
Explain how pipelining improves the performance of a processor.
Explain why registers are important in a RISC processor.
Describe how an interrupt is handled by a RISC processor that uses pipelining.
A program contains a conditional jump. When the jump is taken, the processor's performance drops. Explain why, with reference to the pipeline.
Answer key and marking notes
- RISC has fewer, simpler instructions; CISC has many, more complex instructions.
- RISC instructions are fixed length; CISC instructions are variable length.
- Most RISC instructions take one clock cycle; many CISC instructions take several.
- Any one of: RISC uses only LOAD and STORE to access memory, CISC instructions can use memory operands; RISC has more general-purpose registers; RISC has fewer addressing modes; RISC is easier to pipeline; RISC control units are hardwired, CISC microprogrammed.
- Without pipelining: 12 × 5 = 60 cycles.
- With pipelining: 5 + 12 − 1 = 16 cycles.
- Saving: 60 − 16 = 44 cycles.
- The execution of an instruction is split into stages (such as fetch, decode, operand fetch, execute, write back).
- While one instruction is at one stage, other instructions are at the other stages at the same time.
- Once the pipeline is full, one instruction completes every clock cycle, so more instructions are completed per second (higher throughput).
- RISC uses a load/store design: only LOAD and STORE access memory, other instructions operate on registers.
- Having many general-purpose registers means operands are held in registers, reducing the number of slow memory accesses.
- Register-to-register instructions all take the same short time, which keeps a pipeline flowing; registers between stages pass each partly processed instruction on.
- Several instructions are partly processed in the pipeline when the interrupt is received.
- The instructions in the pipeline are flushed, or those already started are allowed to complete.
- The program counter (address of the next instruction not completed) and the contents of the registers are saved on the stack.
- The ISR is loaded and executed; afterwards the registers are restored and the pipeline is refilled from the saved address.
- Instructions following the jump in memory have already been fetched (and partly decoded) into the pipeline.
- If the jump is taken, those instructions are the wrong ones and must be flushed.
- The pipeline has to refill from the jump target, so several clock cycles pass without an instruction completing.
6 multiple-choice questions on this lesson
From the topic question bank. Assign them in the app for a marked score in your gradebook, or run the topic as a class game.
Which feature is typical of a CISC processor rather than a RISC processor?
- AVariable-length instructions, many of which take several clock cycles
- BOnly LOAD and STORE instructions are allowed to access memory
- CA large number of general-purpose registers and a hardwired control unit
- DA small set of simple instructions, each of a fixed length
A RISC processor has a five-stage pipeline and each stage takes one clock cycle. How many clock cycles does it take to execute 20 instructions with pipelining?
- A24
- B100
- C25
- D20
A pipelined RISC processor flushes its pipeline when an interrupt arrives, then runs the interrupt service routine (ISR). Which address must be saved so the interrupted program can carry on correctly afterwards?
- AThe address of the first instruction that did not complete
- BThe address of the last instruction fetched into the pipeline
- CThe start address of the interrupt service routine
- DThe address of the first instruction of the interrupted program
Which statement about pipelining is correct?
- AEach instruction still passes through every stage, but a new instruction can start every clock cycle
- BEach instruction passes through fewer stages, so every single instruction finishes sooner
- CAll the stages of one instruction are carried out at the same time in different parts of the processor
- DInstructions are executed in a random order so that no stage of the pipeline is ever left idle
A run of instructions takes 23 clock cycles on a four-stage pipeline, with one clock cycle per stage. How many clock cycles would the same run take without pipelining?
- A80
- B92
- C76
- D84
Why is a CISC processor harder to pipeline efficiently than a RISC processor?
- AIts instructions vary in length and in cycles needed, so the stages fall out of step
- BIt has more general-purpose registers, and all of them must be saved at the end of every stage
- CIts instructions cannot be decoded until they have been executed, so stages cannot overlap
- DIts programs contain more instructions, so the pipeline fills up too quickly to be useful
Quiz key
CISC processors have many complex instructions of different lengths, and many take several clock cycles. A load/store design, many general-purpose registers with a hardwired control unit, and a small set of fixed-length instructions are all features of RISC.
With k stages and n instructions a pipeline takes k + n - 1 cycles: 5 + 20 - 1 = 24. 100 (5 x 20) is the time without pipelining. 25 (5 + 20) counts the first instruction twice, and 20 ignores the cycles needed to fill the pipeline.
Flushed instructions are discarded, so the saved program counter must point to the first one that did not complete; after the ISR the pipeline refills from there. Saving the last fetched address would skip the flushed instructions. The ISR's address is where the processor goes, not where it returns to, and restarting the whole program would repeat work already done.
Pipelining overlaps different instructions at different stages, so throughput rises while each instruction still takes all the stages. It does not remove stages or speed up a single instruction. The stages of one instruction still happen one after another, and instructions enter the pipeline in program order.
4 + n - 1 = 23 gives n = 20 instructions, and without pipelining each takes 4 cycles: 20 x 4 = 80. 92 multiplies the pipelined time by 4. 76 uses n = 19 (23 - 4) and 84 uses n = 21 (23 - 4 + 2), both errors in rearranging k + n - 1.
A pipeline needs every stage to take the same time. A CISC instruction that needs many cycles to execute, or that varies in length so it is harder to fetch and decode, holds up the instructions behind it. CISC has fewer registers, not more; decoding always comes before execution; and it is RISC programs, not CISC ones, that contain more instructions.
What to project
The student lesson embeds these tabs. Open them full screen on the projector; every slider has a drag handle on the stage.
Slides for this lesson
A projectable deck for every pack is on the way. Until then, present the student lesson full screen: its sections, figure and lab tabs follow the same order as the plan above.