The shape of the lesson
By the end of the lesson, learners can
- Three buses: A bus is a set of parallel wires connecting the components of a computer.
- What makes it fast: In the lab, change the number of cores, the cache size and the clock speed, and watch how long the same work takes.
- Three ports: A port is the socket on a computer where a peripheral device is plugged in.
- Address bus: one way; n lines address 2n locations.
- Data bus: two way; wider means more bits per transfer.
- Performance: processor type, cores, bus width, clock speed, cache; always give the reason.
- Ports: USB (serial, power, auto-detect), HDMI (digital video and audio), VGA (analogue video only).
One picture every idea returns to
The address bus carries addresses one way, from the processor to memory; with n address lines it can address 2n locations. The data bus carries data and instructions both ways; a wider data bus moves more bits in each transfer. The control bus carries signals such as read, write, clock and interrupt, both ways. Performance depends on the processor type, the number of cores, the bus width, the clock speed and the size of the cache. Ports such as USB, HDMI and VGA connect peripheral devices.
Forty-five minutes, phase by phase
| Time | Phase | What happens in the room | Grouping |
|---|---|---|---|
| 0 to 5 min | Hook: predict | Open with the question in the title, Wider, faster, more.. Data moves around a computer along three buses, and the width of each one sets limits on what the system can do. Put the figure on the board: it is the one picture every idea in the lesson returns to. | Whole class, then pairs |
| 5 to 13 min | Teach and check: Three buses | A bus is a set of parallel wires connecting the components of a computer. Model the worked example Address bus width on the board, one line at a time. Your turn: A data bus is increased from 32 bits to 64 bits. How many transfers are now needed to move 256 bytes, and how many were needed before? | Whole class, then pairs |
| 13 to 21 min | Teach and check: What makes it fast | In the lab, change the number of cores, the cache size and the clock speed, and watch how long the same work takes. Project tab 3 of the lab (Cores, cache and clock speed) and let a student drive it while the class predicts. | Pairs |
| 21 to 30 min | Teach and check: Three ports | A port is the socket on a computer where a peripheral device is plugged in. Your turn: A school wants to connect a laptop to a projector and play a video with sound through the projector's speakers. Which port should it use, and why not VGA? | Connect-Extend-Challenge |
| 30 to 36 min | Check | The four Stage 1 questions from the student lesson, answered on mini whiteboards or by show of fingers. Re-teach the one most get wrong. | Individual, then whole class |
| 36 to 43 min | Plenary | The exam-style questions from Stage 2, one at a time: thirty seconds alone, then a random call. The feedback lines in the key give the examiner's wording. | Individual, random call |
| 43 to 45 min | Exit and homework | Set the worksheet below (6 questions, 16 marks). Learners self-assess against the objectives before they leave. | Individual |
Protect the parts that carry the learning
The sequence carries about fifty minutes of material, so the lab is driven by one student while the class predicts rather than explored freely. Times are a guide.
Protected: the check at 30 minutes. It is the only individual read on whether the key idea landed, and it is not cut.
Cut first if the build overruns: the last check in Three ports, never the check or the plenary.
In a 60 minute block: run worksheet questions 1 to 3 in class as a Rally Coach set and model both the hardest worked example and its check live.
Connect-Extend-Challenge
After the new idea, each student writes three lines: how it connects to what they knew, how it extends their thinking, and what still challenges them. Pairs compare, then the challenges become the plenary.
The full structure, with its variations and the other twelve, is on the cooperative-learning page.
What to head off, and how
| Trap learners fall into | Teaching move that pre-empts it |
|---|---|
| Widening the address bus does not make each transfer bigger: it increases how many memory locations can be addressed. | It is the data bus width that sets how many bits move per transfer. |
| Doubling the cores does not double the speed. | Say that some tasks cannot be split up to run in parallel, and that time is spent coordinating the cores. |
Buses, ports and processor performance: worksheet
6 questions, 16 marks. Written in the style of the papers; no past paper question is reproduced.
Describe the purpose of the address bus, the data bus and the control bus.
A computer has a 20-bit address bus. Each memory location holds one byte. Calculate the maximum amount of memory that can be addressed. Give your answer in MiB.
Explain how increasing (a) the clock speed and (b) the size of the cache can improve the performance of a computer.
A user replaces a dual-core processor with an eight-core processor, but one program runs no faster. Explain why.
For each device, identify the most suitable port and give a reason: (a) a smart TV used as a second screen for a film, (b) a USB flash drive, (c) an old projector with a 15-pin analogue input.
A student writes: "Increasing the width of the address bus means more data is sent with each instruction." Explain why this is incorrect.
Answer key and marking notes
- Address bus: carries the address of the location to be accessed from the processor to memory (one way).
- Data bus: carries data and instructions between the processor, memory and I/O (both ways).
- Control bus: carries control and timing signals, such as read, write and clock, between components.
- 220 = 1 048 576 locations.
- 1 048 576 bytes = 1 MiB.
- (a) The clock produces more pulses per second.
- (a) So more fetch-execute cycles, and so more instructions, are completed per second.
- (b) More frequently used instructions and data can be held in fast cache close to the processor.
- (b) So fewer accesses to slower main memory are needed.
- The program may not be written to be split into tasks or threads that run in parallel.
- So it can only use one core at a time (and the other cores are idle).
- (a) HDMI: carries high-definition digital video and audio together.
- (b) USB: serial data, supplies power and is detected automatically.
- (c) VGA: it carries the analogue video signal the projector expects.
- A wider address bus increases the number of memory locations that can be addressed.
- It is a wider data bus that allows more bits to be transferred at once.
6 multiple-choice questions on this lesson
From the topic question bank. Assign them in the app for a marked score in your gradebook, or run the topic as a class game.
A processor has an 18-bit address bus. How many different memory locations can it address?
- A262 144
- B262 143
- C36
- D131 072
Which bus carries signals in one direction only, and in which direction?
- AThe address bus, from the processor to memory
- BThe data bus, from memory to the processor
- CThe control bus, from the processor to memory
- DThe address bus, from memory to the processor
A teacher must connect a laptop to an old projector whose only input is a 15-pin analogue video socket. Which port should be used?
- AVGA
- BHDMI
- CUSB
- DEthernet
Why does increasing the size of the cache usually improve the performance of a processor?
- AMore frequently used instructions and data can be kept close to the processor, so fewer slow accesses to main memory are needed
- BThe clock can then produce more pulses each second, so more instructions are executed
- CThe processor can then address a larger number of main memory locations
- DEach core can then run two separate programs at exactly the same time
A block of 512 bytes is to be moved between memory and the processor. The data bus is widened from 32 bits to 64 bits. How many transfers are needed now?
- A64
- B8
- C16
- D128
A computer's address bus is widened from 16 lines to 20 lines. The data bus is unchanged. Which statement is correct?
- AIt can address 16 times as many memory locations, but each transfer still moves the same number of bits
- BEach transfer can now move 4 more bits of data, so programs run faster
- CIt can address 4 more memory locations than before
- DThe clock speed rises, because addresses reach memory more quickly
Quiz key
With 18 address lines there are 218 = 262 144 different addresses. 262 143 is the highest address (they are numbered from 0), not the number of locations. 36 comes from 18 × 2 instead of 218, and 131 072 is 217, one line short.
Only the processor sends addresses (from the MAR), so the address bus is one way, processor to memory. The data bus is two way, because data is both read and written. The control bus is also two way: for example, devices send interrupt requests to the processor. Memory never sends addresses back to the processor.
VGA carries an analogue video signal and uses a 15-pin connector, which is what the projector expects. HDMI is digital (video and audio), so it needs a matching digital input. USB is a general purpose serial port for peripherals such as keyboards and flash drives, and Ethernet connects to a network, not a display.
Cache holds copies of frequently used instructions and data, so the processor finds more of what it needs there and waits for slower main memory less often. Clock speed is a separate factor, not changed by the cache. The number of addressable locations depends on the width of the address bus, and running tasks in parallel depends on the number of cores.
512 bytes = 512 × 8 = 4096 bits, and 4096 / 64 = 64 transfers (it was 4096 / 32 = 128 before, so 128 is the old figure). 8 comes from dividing 512 by 64 without converting bytes to bits, and 16 divides 512 by 32, making the same mistake with the old bus width.
220 / 216 = 24 = 16, so 16 times as many locations can be addressed. The number of bits per transfer is set by the data bus, which has not changed. Adding 4 lines multiplies the number of locations by 16; it does not add 4. Bus width has no effect on the clock speed.
What to project
The student lesson embeds these tabs. Open them full screen on the projector; every slider has a drag handle on the stage.
Slides for this lesson
A projectable deck for every pack is on the way. Until then, present the student lesson full screen: its sections, figure and lab tabs follow the same order as the plan above.