The shape of the lesson
By the end of the lesson, learners can
- Reading the notation: Step through the cycle in the lab: each step shows its register transfer.
- Fetch, decode, execute: Describe the cycle in full sentences when asked to "describe", and in notation when the question asks for register transfer notation.
- Trace one instruction: A common question gives you the PC and the contents of memory, then asks for the value in each register after a step.
- MAR ← [PC]: the address of the next instruction.
- PC ← [PC] + 1: point to the following instruction.
- MDR ← [[MAR]]: double brackets, the contents of that address.
- CIR ← [MDR]: then decode, execute and check for interrupts.
One picture every idea returns to
The fetch-execute (F-E) cycle is repeated for every instruction. In register transfer notation, [X] means the contents of X and ← means is copied into. The fetch stage is: MAR ← [PC]; PC ← [PC] + 1; MDR ← [[MAR]]; CIR ← [MDR]. The control unit then decodes the instruction in the CIR and it is executed, which may use memory again through the MAR and MDR and the ALU.
Forty-five minutes, phase by phase
| Time | Phase | What happens in the room | Grouping |
|---|---|---|---|
| 0 to 5 min | Hook: predict | Open with the question in the title, Four lines of notation.. Every instruction a processor runs starts with the same four register transfers. Put the figure on the board: it is the one picture every idea in the lesson returns to. | Whole class, then pairs |
| 5 to 13 min | Teach and check: Reading the notation | Step through the cycle in the lab: each step shows its register transfer. Project tab 2 of the lab (The fetch-execute cycle step by step) and let a student drive it while the class predicts. | Whole class, then pairs |
| 13 to 21 min | Teach and check: Fetch, decode, execute | Describe the cycle in full sentences when asked to "describe", and in notation when the question asks for register transfer notation. | Pairs |
| 21 to 30 min | Teach and check: Trace one instruction | A common question gives you the PC and the contents of memory, then asks for the value in each register after a step. Model the worked example LDD 150 on the board, one line at a time. Your turn: The next instruction, at address 101, is ADD #5. Give the contents of the PC, CIR and ACC after it has been executed. Is the MAR used in the execute stage? | Anticipation / Reaction Guide |
| 30 to 36 min | Check | The four Stage 1 questions from the student lesson, answered on mini whiteboards or by show of fingers. Re-teach the one most get wrong. | Individual, then whole class |
| 36 to 43 min | Plenary | The exam-style questions from Stage 2, one at a time: thirty seconds alone, then a random call. The feedback lines in the key give the examiner's wording. | Individual, random call |
| 43 to 45 min | Exit and homework | Set the worksheet below (6 questions, 18 marks). Learners self-assess against the objectives before they leave. | Individual |
Protect the parts that carry the learning
The sequence carries about fifty minutes of material, so the lab is driven by one student while the class predicts rather than explored freely. Times are a guide.
Protected: the check at 30 minutes. It is the only individual read on whether the key idea landed, and it is not cut.
Cut first if the build overruns: the last check in Trace one instruction, never the check or the plenary.
In a 60 minute block: run worksheet questions 1 to 3 in class as a Rally Coach set and model both the hardest worked example and its check live.
Anticipation / Reaction Guide
Before the lesson, students mark five statements true or false. After the teaching they mark them again and justify any change of mind in one sentence each. The statements come from the examiner traps below.
The full structure, with its variations and the other twelve, is on the cooperative-learning page.
What to head off, and how
| Trap learners fall into | Teaching move that pre-empts it |
|---|---|
| MDR ← [MAR] is wrong: it would copy the address itself. | The instruction comes from the memory location the MAR points to, so it is MDR ← [[MAR]]. |
| The PC is incremented in the fetch stage, not after the instruction has been executed. | This is why a jump instruction simply overwrites the PC. |
The fetch-execute cycle in register transfer notation: worksheet
6 questions, 18 marks. Written in the style of the papers; no past paper question is reproduced.
Complete the fetch stage of the fetch-execute cycle using register transfer notation.
Explain the difference between [MAR] and [[MAR]] in register transfer notation.
The PC holds 40. Address 40 holds LDD 60 and address 60 holds 18. State the contents of the PC, MAR, MDR, CIR and ACC after the instruction has been fetched and executed.
Describe what happens during the decode and execute stages of the cycle for the instruction ADD 75.
Write the execute stage of the instruction JMP 85 in register transfer notation, and explain why the earlier PC ← [PC] + 1 does not cause a problem.
A student writes the fetch stage as: MAR ← [PC]; MDR ← [MAR]; CIR ← [MDR]. Identify the two errors.
Answer key and marking notes
- MAR ← [PC]
- PC ← [PC] + 1
- MDR ← [[MAR]]
- CIR ← [MDR]
- [MAR] is the contents of the MAR, which is a memory address.
- [[MAR]] is the contents of the memory location at the address held in the MAR.
- PC: 41.
- MAR: 60.
- MDR: 18.
- CIR: LDD 60.
- ACC: 18.
- The control unit decodes the instruction in the CIR (opcode ADD, operand 75).
- The address 75 is placed in the MAR and the contents of address 75 are copied into the MDR.
- The ALU adds the contents of the MDR to the accumulator and the result is stored in the ACC.
- PC ← 85.
- The jump overwrites the incremented value, so the next fetch uses address 85.
- MDR ← [MAR] should be MDR ← [[MAR]] (the contents of the address, not the address).
- The step PC ← [PC] + 1 is missing.
6 multiple-choice questions on this lesson
From the topic question bank. Assign them in the app for a marked score in your gradebook, or run the topic as a class game.
In register transfer notation, what does MDR ← [[MAR]] mean?
- AThe contents of the memory location whose address is held in the MAR are copied into the MDR
- BThe address held in the MAR is copied into the MDR
- CThe contents of the MDR are copied into the memory location held in the MAR
- DThe contents of the MAR are added to the contents of the MDR
The PC holds 75 when a fetch begins. What do the MAR and the PC hold at the end of the fetch stage, before the instruction is decoded?
- AMAR 75, PC 76
- BMAR 76, PC 76
- CMAR 75, PC 75
- DMAR 76, PC 75
Which register transfer places the fetched instruction where the control unit can decode it?
- ACIR ← [MDR]
- BCIR ← [[MDR]]
- CMDR ← [CIR]
- DCIR ← [PC]
The PC holds 50. Address 50 holds the instruction JMP 80. What does the PC hold after this instruction has been fetched and executed?
- A80
- B51
- C50
- D81
The PC holds 60. Address 60 holds LDD 90, address 61 holds ADD 91, address 90 holds 14 and address 91 holds 9. Both instructions are fetched and executed. What do the PC, MAR, MDR and ACC hold now?
- APC 62, MAR 91, MDR 9, ACC 23
- BPC 62, MAR 61, MDR ADD 91, ACC 23
- CPC 63, MAR 91, MDR 23, ACC 23
- DPC 62, MAR 91, MDR 9, ACC 9
Which is the correct execute stage, in register transfer notation, for the instruction SUB 151?
- AMAR ← 151; MDR ← [[MAR]]; ACC ← [ACC] − [MDR]
- BMAR ← 151; MDR ← [MAR]; ACC ← [ACC] − [MDR]
- CMDR ← 151; MAR ← [[MDR]]; ACC ← [ACC] − [MAR]
- DMAR ← 151; MDR ← [[MAR]]; ACC ← [MDR] − [ACC]
Quiz key
[MAR] is the address in the MAR, so [[MAR]] is the contents of memory at that address, and the arrow shows it is copied into the MDR. Copying the address itself would be MDR ← [MAR]. The arrow points into the MDR, so data is not being written to memory, and nothing is being added.
MAR ← [PC] copies 75 into the MAR first; then PC ← [PC] + 1 makes the PC 76. The MAR is not incremented, so MAR 76 is wrong, and the PC is incremented during the fetch, not after execution, so PC 75 is wrong.
The instruction arrives in the MDR and is copied into the CIR, so the transfer is CIR ← [MDR]. Double brackets would treat the instruction as an address and fetch something else from memory. MDR ← [CIR] copies in the wrong direction, and the PC holds only an address, not the instruction.
During the fetch the PC is incremented to 51, then the execute stage of JMP 80 is PC ← 80, which overwrites it. 51 forgets the execute stage, 50 forgets both changes, and 81 wrongly adds 1 after the jump.
LDD 90: the fetch leaves PC 61; execution puts 90 in the MAR, 14 in the MDR and 14 in the ACC. ADD 91: the fetch leaves PC 62; execution puts 91 in the MAR, 9 in the MDR, and ACC = 14 + 9 = 23. MAR 61 and MDR ADD 91 are the values after the fetch only. The MDR never receives the result (23), the PC is incremented once per instruction (not 63), and ACC 9 treats ADD as a load.
The address goes to the MAR, the contents of that address come into the MDR (double brackets), and the value is subtracted from the ACC. MDR ← [MAR] would copy the address 151 itself. The address belongs in the MAR, not the MDR. [MDR] − [ACC] subtracts the accumulator from the memory value, the wrong way round.
What to project
The student lesson embeds these tabs. Open them full screen on the projector; every slider has a drag handle on the stage.
Slides for this lesson
A projectable deck for every pack is on the way. Until then, present the student lesson full screen: its sections, figure and lab tabs follow the same order as the plan above.