The shape of the lesson
By the end of the lesson, learners can
- Why interrupt?: Without interrupts, the processor would have to keep checking every device to see whether it needed anything, wasting time.
- When and how it is handled: In the lab, start an interrupt, then fire a higher priority one while the first ISR is running, and watch what is saved on the stack.
- Priorities in action: Questions often describe two or three interrupts arriving close together and ask for the order in which they are serviced.
- Detect: check for interrupts at the end of each F-E cycle.
- Priority: service only if higher than the current task; otherwise it waits.
- Save: registers (including the PC) pushed onto the stack; ISR address into the PC.
- Restore: when the ISR ends, pop the registers and carry on where it stopped.
One picture every idea returns to
An interrupt is a signal from a device or a program to the processor, showing that something needs attention. Interrupts are checked at the end of each fetch-execute cycle. If there is one with a higher priority than the current task, the processor saves the contents of its registers (including the PC) on the stack, loads the start address of the interrupt service routine (ISR) into the PC and runs it. When the ISR finishes, the saved values are restored and the interrupted task carries on from where it stopped.
Forty-five minutes, phase by phase
| Time | Phase | What happens in the room | Grouping |
|---|---|---|---|
| 0 to 5 min | Hook: predict | Open with the question in the title, Excuse me, processor.. A printer runs out of paper, a key is pressed, a program tries to divide by zero. Put the figure on the board: it is the one picture every idea in the lesson returns to. | Whole class, then pairs |
| 5 to 13 min | Teach and check: Why interrupt? | Without interrupts, the processor would have to keep checking every device to see whether it needed anything, wasting time. Your turn: Give one application of interrupts in a multitasking operating system. | Whole class, then pairs |
| 13 to 21 min | Teach and check: When and how it is handled | In the lab, start an interrupt, then fire a higher priority one while the first ISR is running, and watch what is saved on the stack. Project tab 7 of the lab (Interrupts and the ISR) and let a student drive it while the class predicts. | Pairs |
| 21 to 30 min | Teach and check: Priorities in action | Questions often describe two or three interrupts arriving close together and ask for the order in which they are serviced. Model the worked example Order of servicing on the board, one line at a time. Your turn: Why is a stack a suitable structure for saving register contents when interrupts can be nested? | Cooperative Concept Mapping |
| 30 to 36 min | Check | The four Stage 1 questions from the student lesson, answered on mini whiteboards or by show of fingers. Re-teach the one most get wrong. | Individual, then whole class |
| 36 to 43 min | Plenary | The exam-style questions from Stage 2, one at a time: thirty seconds alone, then a random call. The feedback lines in the key give the examiner's wording. | Individual, random call |
| 43 to 45 min | Exit and homework | Set the worksheet below (6 questions, 17 marks). Learners self-assess against the objectives before they leave. | Individual |
Protect the parts that carry the learning
The sequence carries about fifty minutes of material, so the lab is driven by one student while the class predicts rather than explored freely. Times are a guide.
Protected: the check at 30 minutes. It is the only individual read on whether the key idea landed, and it is not cut.
Cut first if the build overruns: the last check in Priorities in action, never the check or the plenary.
In a 60 minute block: run worksheet questions 1 to 3 in class as a Rally Coach set and model both the hardest worked example and its check live.
Cooperative Concept Mapping
Teams receive the key terms on cards and arrange them on a large sheet, drawing and labelling the links. Compare maps between teams before showing the model map.
The full structure, with its variations and the other twelve, is on the cooperative-learning page.
What to head off, and how
| Trap learners fall into | Teaching move that pre-empts it |
|---|---|
| An interrupt is a signal to the processor. | Do not describe it as "an error": many interrupts, such as a key press or a finished print job, are normal events. |
| "The computer stops what it is doing" earns nothing. | Say that the registers are saved (on the stack) so the task can be resumed later, and that the ISR is executed. |
Interrupts: worksheet
6 questions, 17 marks. Written in the style of the papers; no past paper question is reproduced.
State what is meant by an interrupt.
Give three different possible causes of an interrupt.
Describe how the processor detects and handles an interrupt.
Explain why interrupts are only detected at the end of a fetch-execute cycle.
During a program, a printer "paper out" interrupt (priority 2) and a mouse movement interrupt (priority 1) arrive in the same cycle. Then, while the first ISR runs, a hard disk error interrupt (priority 4) arrives. State the order in which the three ISRs start, and the order in which the tasks are completed.
A student says: "When an interrupt happens, the processor stops the program and starts it again from the beginning after the ISR." Explain why this is wrong.
Answer key and marking notes
- A signal sent to the processor (from a device or a program).
- To show that something needs attention / that an event needs processing.
- Hardware, e.g. a printer is out of paper or a key is pressed.
- Software, e.g. division by zero or an illegal memory access.
- Timer, e.g. the end of a time slice (or the user pressing a break key, or power failure).
- At the end of each fetch-execute cycle the processor checks for an interrupt.
- The priority of the interrupt is compared with the current task; if it is higher it is serviced.
- The contents of the registers (including the PC) are saved on the stack.
- The start address of the ISR is loaded into the PC and the ISR is executed.
- When the ISR finishes, the registers are restored from the stack and the interrupted task continues.
- So that the current instruction is completed (not left half executed).
- The register contents are then in a known state that can be saved and resumed correctly.
- ISRs start in the order: printer (priority 2), hard disk error (priority 4, interrupts the printer ISR), mouse (priority 1).
- The hard disk ISR finishes first, then the printer ISR resumes and finishes.
- Then the mouse ISR runs (it is still higher than the program), then the program resumes.
- The program's register contents, including the PC, are saved before the ISR runs.
- They are restored afterwards, so the program continues from where it was interrupted.
6 multiple-choice questions on this lesson
From the topic question bank. Assign them in the app for a marked score in your gradebook, or run the topic as a class game.
At what point does the processor check whether an interrupt has occurred?
- AAt the end of each fetch-execute cycle, before the next instruction is fetched
- BImmediately, even if an instruction is only half executed
- COnly when the running program reaches its END instruction
- DAt the start of every decode stage, before the CIR is read
Which of these events causes a hardware interrupt?
- AA printer runs out of paper
- BA program attempts to divide by zero
- CA program requests a service from the operating system
- DA program tries to access memory it does not own
Which sequence shows the correct order for handling an interrupt that has a higher priority than the current task?
- AFinish the current cycle; save the registers on the stack; load the ISR start address into the PC; run the ISR; restore the registers
- BSave the registers on the stack; finish the current cycle; run the ISR; load the ISR start address into the PC; restore the registers
- CFinish the current cycle; load the ISR start address into the PC; save the registers on the stack; run the ISR; restore the registers
- DFinish the current cycle; run the ISR; save the registers on the stack; restore the registers; load the ISR start address into the PC
What is the main purpose of interrupts?
- ATo let devices and programs signal the processor when they need attention, so it does not waste time repeatedly checking them
- BTo stop a program whenever an error message must be shown to the user
- CTo make the processor restart the current program from its first instruction
- DTo increase the clock speed when a device sends data
A program is running. A mouse interrupt (priority 1, lowest) and a disk error interrupt (priority 3) arrive during the same cycle. While the disk error ISR is running, a keyboard interrupt (priority 2) arrives. In what order are the three ISRs run?
- ADisk error, keyboard, mouse
- BDisk error, mouse, keyboard
- CMouse, disk error, keyboard
- DKeyboard, disk error, mouse
Why is a stack a suitable structure for saving register contents when interrupts can be nested?
- AIt is last in, first out, so the most recently interrupted task is the first one to be restored
- BIt is first in, first out, so the main program is always restored before any ISR
- CIt lets the processor restore any saved task, in any order it chooses
- DIt stores the ISRs themselves, so they can be run without being loaded
Quiz key
Interrupts are checked once the current instruction has been completely executed, at the end of the cycle, so the registers can be saved in a consistent state. Breaking off half way through an instruction would leave it unfinished. Waiting for END would defeat the purpose of interrupts, and the decode stage is part of the cycle, not the point where interrupts are checked.
A printer running out of paper is signalled by a device, so it is a hardware interrupt. Division by zero, a request for an operating system service and an illegal memory access are all generated by the running software, so they are software interrupts.
The current instruction is completed, then the registers (including the PC) are saved, and only then is the PC overwritten with the ISR's start address; after the ISR the saved values are restored. Saving before the cycle ends would save an unfinished state. Loading the ISR address before saving would lose the address where the program stopped, and the ISR cannot run before the PC points to it.
Interrupts let devices and programs tell the processor that something needs attention, so it can do useful work in the meantime instead of polling every device. Many interrupts are normal events, not errors. After servicing an interrupt the program resumes where it stopped, not from the start, and interrupts have nothing to do with the clock speed.
The disk error has the highest priority of the two waiting interrupts, so it is serviced first. The keyboard (2) cannot interrupt the disk ISR (3), so it waits. When the disk ISR ends, the keyboard (2) and mouse (1) are both waiting, and the keyboard has the higher priority, so it goes before the mouse. Servicing in order of arrival ignores the priorities, and the keyboard cannot run first because it had not arrived when the first choice was made.
Nested ISRs must finish in the reverse order to the one in which they started, and a stack returns items last in, first out, which is exactly that order. A first in, first out structure is a queue, which would restore the main program too early. A stack only gives access to its top item, not any item, and it holds saved register values, not the ISR code.
What to project
The student lesson embeds these tabs. Open them full screen on the projector; every slider has a drag handle on the stage.
Slides for this lesson
A projectable deck for every pack is on the way. Until then, present the student lesson full screen: its sections, figure and lab tabs follow the same order as the plan above.