The shape of the lesson
By the end of the lesson, learners can
- The clock: In the lab, change the clock speed, the cache size and the number of cores, and watch how long the same set of tasks takes.
- Cache memory: RAM is fast compared with a hard disk, but slow compared with the CPU.
- More cores: A core is a processing unit with its own control unit, ALU and registers.
- Clock: faster clock, more FDE cycles per second.
- Cache: bigger cache, more frequently used data near the CPU, fewer slow trips to RAM.
- Cores: more cores, more instructions processed at the same time.
- Limits: heat at high clock speeds; not all tasks split across cores; cache is expensive.
One picture every idea returns to
A core is a complete processing unit that can fetch, decode and execute instructions; more cores mean more instructions can be processed at the same time. Cache is a small amount of very fast memory inside or next to the CPU that stores frequently used instructions and data; a bigger cache means fewer slow trips to RAM. The clock sends regular pulses that time each FDE cycle; a higher clock speed (measured in hertz, for example 3.5 GHz) means more cycles per second.
Forty-five minutes, phase by phase
| Time | Phase | What happens in the room | Grouping |
|---|---|---|---|
| 0 to 5 min | Hook: predict | Open with the question in the title, What makes a CPU fast?. Two laptops can have very different speeds even with the same amount of RAM. Put the figure on the board: it is the one picture every idea in the lesson returns to. | Whole class, then pairs |
| 5 to 13 min | Teach and check: The clock | In the lab, change the clock speed, the cache size and the number of cores, and watch how long the same set of tasks takes. Project tab 3 of the lab (Cores, cache and clock) and let a student drive it while the class predicts. | Whole class, then pairs |
| 13 to 21 min | Teach and check: Cache memory | RAM is fast compared with a hard disk, but slow compared with the CPU. Your turn: Why is cache not simply made big enough to replace RAM? | Pairs |
| 21 to 30 min | Teach and check: More cores | A core is a processing unit with its own control unit, ALU and registers. Model the worked example Compare two CPUs on the board, one line at a time. | Mix-Pair-Share |
| 30 to 36 min | Check | The four Stage 1 questions from the student lesson, answered on mini whiteboards or by show of fingers. Re-teach the one most get wrong. | Individual, then whole class |
| 36 to 43 min | Plenary | The exam-style questions from Stage 2, one at a time: thirty seconds alone, then a random call. The feedback lines in the key give the examiner's wording. | Individual, random call |
| 43 to 45 min | Exit and homework | Set the worksheet below (6 questions, 14 marks). Learners self-assess against the objectives before they leave. | Individual |
Protect the parts that carry the learning
The sequence carries about fifty minutes of material, so the lab is driven by one student while the class predicts rather than explored freely. Times are a guide.
Protected: the check at 30 minutes. It is the only individual read on whether the key idea landed, and it is not cut.
Cut first if the build overruns: the last check in More cores, never the check or the plenary.
In a 60 minute block: run worksheet questions 1 to 3 in class as a Rally Coach set and model both the hardest worked example and its check live.
Mix-Pair-Share
Students mix around the room until you call pair; they pair with the nearest classmate, discuss the prompt, then mix again. Three prompts of rising difficulty, three different partners.
The full structure, with its variations and the other twelve, is on the cooperative-learning page.
What to head off, and how
| Trap learners fall into | Teaching move that pre-empts it |
|---|---|
| Clock speed is not a measure of memory. 3.5 GHz describes how often the CPU's clock ticks, not how much it can store. | Return to The clock: ask a pair to state the correct version and show it on the lab before moving on. |
| Always say how the factor improves performance: "more cores, so more instructions can be processed at the same time", not just "more cores make it faster". | Return to More cores: ask a pair to state the correct version and show it on the lab before moving on. |
Cores, cache and clock speed: worksheet
6 questions, 14 marks. Written in the style of the papers; no past paper question is reproduced.
Explain how increasing the clock speed of a CPU can improve its performance.
Describe what is meant by cache and explain how its size affects performance.
Explain how having more cores can affect the performance of a CPU.
A school compares CPU X (2 cores, 4.0 GHz, 6 MiB cache) and CPU Y (6 cores, 3.2 GHz, 12 MiB cache) for running several programs at once. Recommend one and justify your choice.
Give two reasons why doubling the number of cores may not double the performance of a computer.
A shop assistant says a computer with a 3 GHz CPU "can store 3 gigabytes". Explain the mistake.
Answer key and marking notes
- The clock sends more pulses per second.
- So more fetch-decode-execute cycles (instructions) are carried out per second.
- Cache is a small amount of very fast memory in or near the CPU.
- It stores frequently used instructions and data.
- A larger cache stores more of them, so the CPU makes fewer slower fetches from RAM.
- Each core can process instructions independently.
- So more instructions can be processed at the same time (simultaneously).
- CPU Y.
- It has more cores, so more programs/instructions can be processed at the same time.
- It has a larger cache, so fewer slower fetches from RAM (even though X has a faster clock).
- Some tasks/programs cannot be split up to run on several cores.
- Time is spent communicating and sharing data between cores (or the software is not written to use multiple cores).
- 3 GHz is the clock speed: 3 billion clock cycles per second.
- It describes processing speed, not storage capacity.
6 multiple-choice questions on this lesson
From the topic question bank. Assign them in the app for a marked score in your gradebook, or run the topic as a class game.
What is cache memory?
- Aa small amount of very fast memory in or next to the CPU that stores frequently used instructions and data
- Ba large area of secondary storage used as extra RAM when RAM becomes full
- Ca register inside the CPU that holds the address of the next instruction
- Da type of ROM that stores the start-up instructions for the computer
A CPU has a clock speed of 2.5 GHz. How many clock cycles does it carry out each second?
- A2 500 000 000
- B2 500 000
- C2 500
- D250 000 000
Which change to a CPU is most likely to mean that more fetch-decode-execute cycles are carried out each second by each core?
- Aincreasing the clock speed from 2.8 GHz to 3.6 GHz
- Bincreasing the RAM from 8 GiB to 16 GiB
- Creplacing the hard disk drive with a solid-state drive
- Dincreasing the secondary storage from 512 GB to 1 TB
A computer's CPU is upgraded from 2 cores to 4 cores with the same clock speed and cache. A program does not run twice as fast. Which is the best explanation?
- ASome tasks cannot be split up, and cores spend time communicating and sharing data
- BEach extra core lowers the clock speed of the other cores by half
- CExtra cores only increase the amount of cache, not the processing done
- DCores can only be used by the operating system, not by programs
A CPU has a clock speed of 4 GHz. How long does one clock cycle take?
- A0.25 nanoseconds
- B4 nanoseconds
- C0.4 nanoseconds
- D25 nanoseconds
CPU A: 4 cores, 2.0 GHz, 4 MiB cache. CPU B: 2 cores, 3.5 GHz, 8 MiB cache. A program that has not been written to use more than one core is run on each. Which CPU is likely to run it faster, and why?
- ACPU B: the program uses one core, and B's faster clock and bigger cache help that core
- BCPU A: four cores always process instructions faster than two cores
- CCPU A: a lower clock speed keeps it cooler, so it never slows down
- DCPU B: two cores are always faster than four because they communicate less
Quiz key
Cache is small, very fast memory close to the CPU holding the instructions and data used most often, so fewer slow trips to RAM are needed. Secondary storage used as extra RAM is virtual memory. The address of the next instruction is in the PC, a register. Start-up instructions are kept in ROM.
1 GHz is 1 000 000 000 (109) cycles per second, so 2.5 GHz is 2.5 × 109 = 2 500 000 000 cycles per second. 2 500 000 treats giga as mega (106), 2 500 treats it as kilo, and 250 000 000 has the decimal point in the wrong place.
The clock speed is the number of cycles per second, so a faster clock means each core carries out more FDE cycles every second. More RAM, an SSD or more storage may make the whole computer feel quicker or hold more, but none of them changes how many cycles the CPU completes per second.
More cores let more instructions be processed at the same time, but only if the work can be divided; some steps must happen in order, and the cores lose time co-ordinating and sharing data. Adding cores does not halve the clock speed. Each core is a processing unit with its own CU, ALU and registers, not just extra cache. Programs can use several cores if written to do so.
4 GHz is 4 × 109 cycles per second, so one cycle lasts 1 ÷ (4 × 109) = 0.25 × 10−9 s = 0.25 ns. 4 ns multiplies instead of dividing. 0.4 ns and 25 ns come from misplacing the decimal point in 1 ÷ 4.
A program written for one core gains nothing from extra cores, so compare a single core: B's clock does more cycles per second and its larger cache means fewer slow fetches from RAM, so B should be faster. More cores only help when the software can use them, so 'always faster' is wrong. A cooler CPU is not a reason for faster processing here, and fewer cores are not 'always' faster either: for multi-core software, A could win.
What to project
The student lesson embeds these tabs. Open them full screen on the projector; every slider has a drag handle on the stage.
Slides for this lesson
A projectable deck for every pack is on the way. Until then, present the student lesson full screen: its sections, figure and lab tabs follow the same order as the plan above.