The shape of the lesson
By the end of the lesson, learners can
- The fetch stage: Step through the cycle in the lab and watch the values move between registers.
- Decode and execute: Now the CPU knows what the instruction is, but not yet what it means.
- Order matters: Exam questions often ask you to describe the cycle, or to put the steps in order.
- Fetch: PC → MAR → address bus; data bus → MDR → CIR; PC incremented.
- Decode: the CU decodes the instruction in the CIR.
- Execute: the CU sends signals; the ALU calculates; the result goes in the ACC.
- Marks: one per correct step, in order, naming the register or bus.
One picture every idea returns to
The CPU runs a program by repeating the fetch-decode-execute (FDE) cycle. Fetch: the address in the PC is copied to the MAR and sent along the address bus; the instruction at that address in RAM comes back along the data bus to the MDR and is copied to the CIR; the PC is incremented. Decode: the CU decodes the instruction in the CIR. Execute: the CU sends signals to carry it out, and the ALU does any calculation, with the result stored in the ACC.
Forty-five minutes, phase by phase
| Time | Phase | What happens in the room | Grouping |
|---|---|---|---|
| 0 to 5 min | Hook: predict | Open with the question in the title, Fetch, decode, repeat.. A CPU does one simple thing billions of times a second: it fetches an instruction from memory, works out what it means and carries it out. Put the figure on the board: it is the one picture every idea in the lesson returns to. | Whole class, then pairs |
| 5 to 13 min | Teach and check: The fetch stage | Step through the cycle in the lab and watch the values move between registers. Project tab 2 of the lab (Fetch-decode-execute step by step) and let a student drive it while the class predicts. | Whole class, then pairs |
| 13 to 21 min | Teach and check: Decode and execute | Now the CPU knows what the instruction is, but not yet what it means. Model the worked example Trace one instruction on the board, one line at a time. Your turn: After the fetch stage above, which register holds the instruction ADD 26, and what value is in the PC? | Pairs |
| 21 to 30 min | Teach and check: Order matters | Exam questions often ask you to describe the cycle, or to put the steps in order. | Think-Pair-Share |
| 30 to 36 min | Check | The four Stage 1 questions from the student lesson, answered on mini whiteboards or by show of fingers. Re-teach the one most get wrong. | Individual, then whole class |
| 36 to 43 min | Plenary | The exam-style questions from Stage 2, one at a time: thirty seconds alone, then a random call. The feedback lines in the key give the examiner's wording. | Individual, random call |
| 43 to 45 min | Exit and homework | Set the worksheet below (6 questions, 15 marks). Learners self-assess against the objectives before they leave. | Individual |
Protect the parts that carry the learning
The sequence carries about fifty minutes of material, so the lab is driven by one student while the class predicts rather than explored freely. Times are a guide.
Protected: the check at 30 minutes. It is the only individual read on whether the key idea landed, and it is not cut.
Cut first if the build overruns: the last check in Order matters, never the check or the plenary.
In a 60 minute block: run worksheet questions 1 to 3 in class as a Rally Coach set and model both the hardest worked example and its check live.
Think-Pair-Share
Pose the question, give thirty seconds of silent thinking, then a minute to compare with a partner before a few pairs share with the class. The silent minute is the part that cannot be cut.
The full structure, with its variations and the other twelve, is on the cooperative-learning page.
What to head off, and how
| Trap learners fall into | Teaching move that pre-empts it |
|---|---|
| The PC is incremented during the fetch stage, ready for the next cycle. | It is not incremented after the instruction is executed. |
| Name the registers in full or by their correct initials. "It goes to the register" does not earn the mark: say "copied from the MDR to the CIR". | Return to Order matters: ask a pair to state the correct version and show it on the lab before moving on. |
The fetch-decode-execute cycle: worksheet
6 questions, 15 marks. Written in the style of the papers; no past paper question is reproduced.
Describe the stages of the fetch part of the fetch-decode-execute cycle.
State what happens during the decode and execute stages.
The PC holds 30. Address 30 holds the instruction LDA 34, which loads the value at address 34 into the ACC. Address 34 holds 9. State the contents of the PC, the CIR and the ACC after this instruction has been executed.
Explain why the program counter is incremented during the fetch stage.
Identify the bus used to send the address from the MAR to memory, and the bus used to return the instruction.
A student writes: "In the fetch stage the instruction goes from RAM straight into the CIR." Explain what is missing.
Answer key and marking notes
- The address in the PC is copied to the MAR.
- The address is sent to RAM along the address bus (with a read signal on the control bus).
- The instruction at that address is sent along the data bus to the MDR.
- The instruction is copied from the MDR to the CIR, and the PC is incremented.
- Decode: the control unit decodes the instruction in the CIR.
- Execute: the CU sends signals to carry out the instruction (the ALU performs any calculation and the result is stored in the ACC).
- PC: 31.
- CIR: LDA 34.
- ACC: 9.
- So that it holds the address of the next instruction.
- Ready for the next fetch, so instructions are run in sequence.
- Address bus.
- Data bus.
- The instruction first arrives in the MDR (along the data bus).
- It is then copied from the MDR to the CIR.
6 multiple-choice questions on this lesson
From the topic question bank. Assign them in the app for a marked score in your gradebook, or run the topic as a class game.
What is the first thing that happens in the fetch stage of the fetch-decode-execute cycle?
- AThe address in the PC is copied into the MAR
- BThe instruction in the CIR is decoded by the control unit
- CThe instruction in the MDR is copied into the CIR
- DThe PC is incremented to point to the next instruction
During the decode stage, which register holds the instruction that the control unit is decoding?
- Acurrent instruction register (CIR)
- Bprogram counter (PC)
- Cmemory address register (MAR)
- Daccumulator (ACC)
Which sequence shows the fetch stage in the correct order?
- APC → MAR; address sent to RAM; instruction to MDR; MDR → CIR; PC incremented
- BPC → MDR; address sent to RAM; instruction to MAR; MAR → CIR; PC incremented
- CPC incremented; PC → CIR; address sent to RAM; instruction to MDR; MDR → MAR
- DMAR → PC; instruction to CIR; CIR → MDR; address sent to RAM; PC incremented
At which point in the cycle is the program counter incremented?
- Aduring the fetch stage, after its value has been copied to the MAR
- Bduring the execute stage, after the result is stored in the ACC
- Cduring the decode stage, while the CU decodes the instruction
- Donly when the instruction is a jump to a new address
The PC holds 40 and the ACC holds 6. The memory contents are shown. After one complete fetch-decode-execute cycle, what values are in the ACC and the PC?
- AACC 15, PC 41
- BACC 15, PC 40
- CACC 51, PC 41
- DACC 9, PC 41
The PC holds 20. LDA loads a value into the ACC, ADD adds a value to the ACC and STO stores the ACC at an address. After the CPU has completed three fetch-decode-execute cycles, what is stored at address 27, and what is in the PC?
- Aaddress 27 holds 12; PC holds 23
- Baddress 27 holds 12; PC holds 22
- Caddress 27 holds 7; PC holds 23
- Daddress 27 holds 51; PC holds 23
Quiz key
Fetch begins by copying the address of the next instruction from the PC into the MAR, so it can be sent along the address bus. Copying from the MDR to the CIR and incrementing the PC also happen during fetch, but later, once the instruction has arrived. Decoding the CIR is the decode stage, after fetch.
At the end of fetch the instruction is copied from the MDR into the CIR, and the CU decodes it there. The PC by then holds the address of the next instruction, the MAR holds an address rather than an instruction, and the ACC holds results of calculations.
The address of the next instruction goes from the PC to the MAR and out along the address bus; the instruction comes back along the data bus into the MDR and is copied to the CIR; then the PC is incremented. The second option swaps the jobs of the MAR and MDR. The third increments the PC before using it, so the wrong instruction would be fetched, and the fourth copies values backwards and sends the address last.
Once the PC's value has been copied into the MAR, the PC is incremented during fetch so it already points at the next instruction. It is a common error to say it is incremented after execution. Decoding is the CU's job and does not involve the PC. Every fetch increments the PC; a jump instruction would then change it again.
Fetch: 40 goes to the MAR, ADD 45 arrives in the MDR and CIR, and the PC becomes 41. Execute: 45 goes to the MAR, the value 9 comes back to the MDR, and the ALU adds 6 + 9 = 15 into the ACC. ACC 51 adds the address 45 instead of its contents. ACC 9 loads the value instead of adding it. PC 40 forgets that the PC is incremented during fetch.
Cycle 1 (address 20): ACC = 7, PC = 21. Cycle 2 (address 21): ACC = 7 + 5 = 12, PC = 22. Cycle 3 (address 22): 12 is stored at address 27, PC = 23. PC 22 forgets the increment in the third fetch. 7 stores the value before the ADD has happened. 51 adds the addresses 25 and 26 instead of their contents.
What to project
The student lesson embeds these tabs. Open them full screen on the projector; every slider has a drag handle on the stage.
Slides for this lesson
A projectable deck for every pack is on the way. Until then, present the student lesson full screen: its sections, figure and lab tabs follow the same order as the plan above.