The shape of the lesson
By the end of the lesson, learners can
- What the CPU does: Explore each part in the lab to see its job.
- Units and registers: A register is a tiny, very fast store inside the CPU that holds one value.
- Three buses: A bus is a set of parallel wires that carries signals between the CPU, memory and input/output devices.
- Addresses: PC (next instruction) and MAR (location being accessed now).
- Contents: MDR (data or instruction moving to or from memory), CIR (current instruction), ACC (result).
- Units: CU decodes and controls; ALU does arithmetic and logic.
- Buses: address (one way), data and control (two way).
One picture every idea returns to
The central processing unit (CPU) processes the instructions and data that are input into the computer so that the result can be output. A microprocessor is a type of integrated circuit with the CPU on a single chip. In a Von Neumann architecture the instructions and data are both stored in the same memory (RAM) and travel along the same buses. The CPU contains the control unit (CU), the arithmetic logic unit (ALU) and registers: PC, MAR, MDR, CIR and ACC.
Forty-five minutes, phase by phase
| Time | Phase | What happens in the room | Grouping |
|---|---|---|---|
| 0 to 5 min | Hook: predict | Open with the question in the title, Inside the processor.. Every program you run is carried out by the central processing unit, one tiny instruction at a time. Put the figure on the board: it is the one picture every idea in the lesson returns to. | Whole class, then pairs |
| 5 to 13 min | Teach and check: What the CPU does | Explore each part in the lab to see its job. Project tab 1 of the lab (Von Neumann architecture) and let a student drive it while the class predicts. | Whole class, then pairs |
| 13 to 21 min | Teach and check: Units and registers | A register is a tiny, very fast store inside the CPU that holds one value. Model the worked example Name the register on the board, one line at a time. Your turn: An instruction tells the CPU to add two numbers. Which unit does the addition, and which register will hold the answer? | Pairs |
| 21 to 30 min | Teach and check: Three buses | A bus is a set of parallel wires that carries signals between the CPU, memory and input/output devices. Your turn: Why is the address bus one-directional? | Rally Robin |
| 30 to 36 min | Check | The four Stage 1 questions from the student lesson, answered on mini whiteboards or by show of fingers. Re-teach the one most get wrong. | Individual, then whole class |
| 36 to 43 min | Plenary | The exam-style questions from Stage 2, one at a time: thirty seconds alone, then a random call. The feedback lines in the key give the examiner's wording. | Individual, random call |
| 43 to 45 min | Exit and homework | Set the worksheet below (6 questions, 15 marks). Learners self-assess against the objectives before they leave. | Individual |
Protect the parts that carry the learning
The sequence carries about fifty minutes of material, so the lab is driven by one student while the class predicts rather than explored freely. Times are a guide.
Protected: the check at 30 minutes. It is the only individual read on whether the key idea landed, and it is not cut.
Cut first if the build overruns: the last check in Three buses, never the check or the plenary.
In a 60 minute block: run worksheet questions 1 to 3 in class as a Rally Coach set and model both the hardest worked example and its check live.
Rally Robin
Pairs take turns to say one item each, back and forth: a definition, a unit, a step of the method. Keep it fast and oral; the point is retrieval, not writing.
The full structure, with its variations and the other twelve, is on the cooperative-learning page.
What to head off, and how
| Trap learners fall into | Teaching move that pre-empts it |
|---|---|
| "The CPU stores all the files" is wrong. | The CPU processes; files are kept in storage. Registers inside the CPU hold only a few values at a time. |
| Do not mix up the MAR and the MDR. | The MAR holds an address (where); the MDR holds data or an instruction (what). |
| The data bus carries instructions as well as data, because in a Von Neumann computer both are stored in the same memory. | Return to Three buses: ask a pair to state the correct version and show it on the lab before moving on. |
The CPU and Von Neumann architecture: worksheet
6 questions, 15 marks. Written in the style of the papers; no past paper question is reproduced.
State the role of the central processing unit (CPU) in a computer.
Name the register described in each case.
(a) Holds the address of the next instruction.
(b) Holds the result of a calculation.
(c) Holds the address of the location about to be accessed.
(d) Holds the instruction being decoded.
Explain what is meant by a Von Neumann architecture.
Identify the three buses in a Von Neumann computer and state what each one carries.
Describe the purpose of the arithmetic logic unit (ALU).
A student writes: "The MAR stores the data that is read from memory." Explain the mistake.
Answer key and marking notes
- It processes instructions and data that are input into the computer.
- So that the result can be output (by fetching, decoding and executing instructions).
- (a) Program counter (PC).
- (b) Accumulator (ACC).
- (c) Memory address register (MAR).
- (d) Current instruction register (CIR).
- Instructions and data are stored together in the same memory.
- They are fetched by the CPU along the same buses, one after another.
- Address bus: carries memory addresses (from the CPU to memory).
- Data bus: carries data and instructions (both ways).
- Control bus: carries control signals such as read, write and the clock.
- It carries out arithmetic calculations, such as addition and subtraction.
- It carries out logic operations, such as AND, OR and comparisons.
- The MAR stores the address of the memory location, not the data.
- The data read from memory is stored in the MDR.
6 multiple-choice questions on this lesson
From the topic question bank. Assign them in the app for a marked score in your gradebook, or run the topic as a class game.
Which register holds the address of the next instruction to be fetched?
- Aprogram counter (PC)
- Bmemory address register (MAR)
- Ccurrent instruction register (CIR)
- Daccumulator (ACC)
What is the purpose of the memory data register (MDR)?
- AIt holds the data or instruction just read from memory, or about to be written to memory
- BIt holds the address of the memory location about to be read from or written to
- CIt holds the instruction that is currently being decoded and executed
- DIt holds the result of a calculation carried out by the ALU
Which bus carries signals in one direction only, from the CPU to memory?
- Aaddress bus
- Bdata bus
- Ccontrol bus
- Dsystem clock bus
Which statement describes a Von Neumann architecture?
- AProgram instructions and data are stored in the same memory and travel along the same buses
- BProgram instructions are stored in ROM and data is stored in RAM, using separate buses
- CInstructions are kept in the CPU's registers so that they never need to be fetched
- DData is stored in the CPU and instructions are stored in secondary storage
The CPU reads the value 7 from memory address 25. Immediately after the value arrives in the CPU, what do the MAR and the MDR hold?
- AMAR holds 25, MDR holds 7
- BMAR holds 7, MDR holds 25
- CMAR holds 25, MDR holds 25
- DMAR holds 7, MDR holds 7
A student says: "The data bus only carries data, never instructions." Why is this wrong in a Von Neumann computer?
- AInstructions are stored in the same memory as data, so they are also fetched along the data bus
- BInstructions are sent along the address bus, so the data bus carries data and addresses
- CInstructions are generated by the control unit, so they never use any bus
- DThe data bus carries instructions only when the control bus is busy
Quiz key
The PC always holds the address of the next instruction to be fetched. The MAR holds the address that is about to be read from or written to right now (the PC's value is copied into it during fetch), so it is not where the 'next' address is kept. The CIR holds the instruction itself, not an address, and the ACC holds results from the ALU.
The MDR is the CPU's buffer for whatever travels along the data bus: data or an instruction that has just been read from memory, or data waiting to be written. Holding an address is the job of the MAR, holding the instruction being decoded is the CIR, and holding the ALU's results is the accumulator.
Only the CPU sends memory addresses (from the MAR), so the address bus is one-way. The data bus is two-way because data and instructions are both read from and written to memory. The control bus is also two-way, carrying signals such as read, write and clock. 'System clock bus' is not one of the three buses: clock signals travel on the control bus.
In a Von Neumann computer a program's instructions and its data share one main memory (RAM) and the same buses, and the CPU fetches them one after another. Keeping instructions and data in separate memories with separate buses is a different design. Registers hold only a few values at a time, so a program cannot live there, and the CPU cannot run instructions straight from secondary storage.
The address 25 is placed in the MAR and sent along the address bus; the contents of that location, 7, come back along the data bus into the MDR. Swapping them mixes up 'where' (MAR) and 'what' (MDR). The MAR cannot hold the data value 7, and the MDR does not hold a copy of the address.
Because instructions and data share one memory, an instruction is fetched exactly like data: its address goes out on the address bus and the instruction comes back on the data bus into the MDR, then to the CIR. The address bus carries addresses only. The control unit decodes instructions but does not create them; they come from the program in memory. The buses do not stand in for each other when one is busy.
What to project
The student lesson embeds these tabs. Open them full screen on the projector; every slider has a drag handle on the stage.
Slides for this lesson
A projectable deck for every pack is on the way. Until then, present the student lesson full screen: its sections, figure and lab tabs follow the same order as the plan above.